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chevalier
Mentor
Mentor
9,156 Views
Registered: ‎10-07-2011

Pipeline throughput reduction

Hi folks,

 

I'm (still) trying to create a vector averaging function using HLS C++ (Win 7-64 and Vivado 2013.4). The code I wrote is C-simulating and synthetizing OK, but cosim is failing with the following message:

 

@W [SIM-201] RTL produces unknown value 'X' on port 'r_data_V', possible cause: There are uninitialized variables in the C design.

 

My function is implemented as a pipeline, with II=1. However, it outputs a vector only every Nth input vector (ie it is NOT a rolling average). The function is summing N vectors and once the accumulation is completed, it divides the accumulated sum by N and output a single vector. Hence, the output throughput is N-times less than the input throughput.

 

My function is defined as follow:

 

void          VectorAveraging(tAXIS *x,tAXIS *r,ap_uint<8> N)

 

where:

 

typedef struct {

    ap_uint<16>     data;        // AXI4-Stream <data> bus

    ap_uint<1>       last;         // AXI4-Stream <last> signal

}  tAXIS;

 

The function is called for each incoming data beat and shall output a result at the same pace. However, a valid vector is output only once every Nth input vector, meaning that the AXI4-Stream TVALID signal is NOT asserted every time the function returns, which I think is causing the above message.

 

Is there a way (directive or pragma) I could use within HLS to let the tool know NOT to expect a VALID result everytime the function returns?

 

Thanks!

 

Claude

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4 Replies
brucey
Xilinx Employee
Xilinx Employee
9,123 Views
Registered: ‎03-24-2010

Hello, you may try "set_directive_occurrence", but I'm not sure if it suits your situation. You may refer to UG902 for details for this directive.

Regards,
brucey
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chevalier
Mentor
Mentor
9,115 Views
Registered: ‎10-07-2011

Hello Brucey,

 

Thanks for letting me know about the "set_directive_occurence" directive. It will certainly be helpful in the future but unfortunately, doesn't seem well suited for my current application. This is because the -cycle option need to be specified at compile time while my application would need it to be runtime configurable.

 

Cheers!

 

Claude

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herver
Xilinx Employee
Xilinx Employee
9,048 Views
Registered: ‎08-17-2011

hello Claude,

did you you check the design examples maybe there's something that helps in C:\Xilinx\Vivado_HLS\2013.4\examples\design..

i'm not sure i understand the issues , can you maybe post as testcase + TB so we can run this through the tools.
- Hervé

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neeruajith
Visitor
Visitor
1,052 Views
Registered: ‎06-12-2018

I am also facing a similar issue. Did you solve it?

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