We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎01-15-2019

Pipeline with feedback over multiple clocks

Hello. I need to implement the following structure in HLS:structure_with_feedback.jpgHere is an example implementation for this structure (my actual function is more complicated):


#ifndef _TOP_HPP_
#define _TOP_HPP_
#include "ap_fixed.h"
void top_func(int in, int *out);


#include "top.hpp"
int foo(int x, int y){
    #pragma HLS pipeline ii=1
    #pragma HLS latency min=5 max=5
    return x + y;
void top_func(int in, int *out){
    #pragma HLS pipeline ii=1
    int y = 0;
    static int y_feed_back= 0;
    #pragma HLS DEPENDENCE variable=y_feed_back inter false 
    y = foo(in, y_feed_back);
    y_feed_back = y;
    *out = y;


#include <iostream>
#include "top.hpp"
int main(){
    int out;
    for(int i; i<20; ++i){
        std::cout<<out<<" ";
    return 0;


open_project hls_proj
set_top top_func
add_files top.cpp 
add_files top.hpp
add_files -tb tb.cpp -cflags "-std=c++14"
open_solution -reset "solution1"
set_part {xc7z020clg484-3} -tool vivado
create_clock -period 200MHz -name default
cosim_design -trace_level all -rtl verilog

And the console output of co-simulation is:

0 1 2 3 4 5 6 7 9 11 13 15 17 19 21 24 27 30 33 36

Which is just fine, and exactly what I need (since the signal needs 7 clocks to propagate to feedback output). But the output of the csim is:

0 1 3 6 10 15 21 28 36 45 55 66 78 91 105 120 136 153 171 190

What is to be expected (normal C++ execution), but is not what happens on later hardware.

My question is if I can somehow obtain the correct result in csim for this case?




0 Kudos
2 Replies
Registered: ‎05-31-2017

Re: Pipeline with feedback over multiple clocks

HI paul.kuehne@barkhauseninstitut.org ,

According to your code C simulation will always gives the same result

0 1 3 6 10 15 21 28 36 45 55 66 78 91 105 120 136 153 171 190

This is because in Csimulation the y_feedback gets updated for every input.

Can you please elaborate more on your application ? I mean do you want the y_feeback signal to get updated only once for 7 inputs ?

0 Kudos
Registered: ‎01-15-2019

Re: Pipeline with feedback over multiple clocks

Hello shameera,

Thank you for your replay!

I mean, y_feed_back register should be updated every clock, but the function foo has a latency of 5 clocks. Therefore in the first 5 clocks the output of foo and input of the y_feed_back register has no valid values. In the 6th clock it becomes 0, and in the 7th clock it becomes 1 and so on (the output of y_feed_back register becomes 0 in 7th clock and 1 in 8th clock).  This behavior is reached here by directive "#pragma HLS DEPENDENCE variable = y_feed_back inter false". That's exactly what I need and expect.Capture.PNG
But in the C-simulation, the pragmas are not taken into account, so the behavior is different than by co-simulation.
In order to achieve the same behavior I should probably put the function foo and the register y_feed_back in different threads. But I think multithreads are not supported by the synthesis.


0 Kudos