11-10-2020 05:31 AM
Silly question.... is not possible to include RTL primitives like ISERDES in HLS, am I right?
11-10-2020 08:32 AM - edited 11-10-2020 08:32 AM
Hello @joancab , @dsakjl is correct that the black box method allows the inclusion of RTL into the HLS flow. However, I want to point something out about the intent of this flow. The idea of the black box flow is that you have an algorithm that you have optimized in RTL, but that you want to include that in the HLS flow rather than connect at the IPI level. This allows you to include an behavioral model of the algorithm for C Simulation and CoSim stages of HLS, and lets the tool instantiate that RTL as a black box. The simulation aspect here is the greatest benefit as you don't have to develop a testbench and perform an RTL simulation of that algorithm combined with the exported HLS IP at the IPI level to ensure it works with your HLS IP. However, this is not meant for including things like SERDES or MMCM's etc. Those are best instantiated at the top level of the design and not inside a HLS IP. I think this goes along with the idea that HLS is meant to create IP's, or kernels, and not an entire system design.
OK, I just wanted to add on to this discussion.
Scott
11-10-2020 07:37 AM
11-10-2020 08:32 AM - edited 11-10-2020 08:32 AM
Hello @joancab , @dsakjl is correct that the black box method allows the inclusion of RTL into the HLS flow. However, I want to point something out about the intent of this flow. The idea of the black box flow is that you have an algorithm that you have optimized in RTL, but that you want to include that in the HLS flow rather than connect at the IPI level. This allows you to include an behavioral model of the algorithm for C Simulation and CoSim stages of HLS, and lets the tool instantiate that RTL as a black box. The simulation aspect here is the greatest benefit as you don't have to develop a testbench and perform an RTL simulation of that algorithm combined with the exported HLS IP at the IPI level to ensure it works with your HLS IP. However, this is not meant for including things like SERDES or MMCM's etc. Those are best instantiated at the top level of the design and not inside a HLS IP. I think this goes along with the idea that HLS is meant to create IP's, or kernels, and not an entire system design.
OK, I just wanted to add on to this discussion.
Scott
11-10-2020 08:47 AM
Hi @scampbell ,
thank you for the explanation.
I can't find RTL blackbox feature in Vitis HLS tool documentation. Will it be added in a future release?
11-10-2020 08:53 AM