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joancab
Teacher
Teacher
788 Views
Registered: ‎05-11-2015

Primitives in HLS

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Silly question.... is not possible to include RTL primitives like ISERDES in HLS, am I right?

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scampbell
Moderator
Moderator
750 Views
Registered: ‎10-04-2011

Hello @joancab , @dsakjl  is correct that the black box method allows the inclusion of RTL into the HLS flow. However, I want to point something out about the intent of this flow. The idea of the black box flow is that you have an algorithm that you have optimized in RTL, but that you want to include that in the HLS flow rather than connect at the IPI level. This allows you to include an behavioral model of the algorithm for C Simulation and CoSim stages of HLS, and lets the tool instantiate that RTL as a black box. The simulation aspect here is the greatest benefit as you don't have to develop a testbench and perform an RTL simulation of that algorithm combined with the exported HLS IP at the IPI level to ensure it works with your HLS IP. However, this is not meant for including things like SERDES or MMCM's etc. Those are best instantiated at the top level of the design and not inside a HLS IP. I think this goes along with the idea that HLS is meant to create IP's, or kernels, and not an entire system design. 

OK, I just wanted to add on to this discussion.
Scott

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4 Replies
dsakjl
Voyager
Voyager
770 Views
Registered: ‎07-20-2018

Hi @joancab ,

you can check for "RTL Blackbox" in Vivado HLS documentation:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug902-vivado-high-level-synthesis.pdf

(UG902, page 584).

scampbell
Moderator
Moderator
751 Views
Registered: ‎10-04-2011

Hello @joancab , @dsakjl  is correct that the black box method allows the inclusion of RTL into the HLS flow. However, I want to point something out about the intent of this flow. The idea of the black box flow is that you have an algorithm that you have optimized in RTL, but that you want to include that in the HLS flow rather than connect at the IPI level. This allows you to include an behavioral model of the algorithm for C Simulation and CoSim stages of HLS, and lets the tool instantiate that RTL as a black box. The simulation aspect here is the greatest benefit as you don't have to develop a testbench and perform an RTL simulation of that algorithm combined with the exported HLS IP at the IPI level to ensure it works with your HLS IP. However, this is not meant for including things like SERDES or MMCM's etc. Those are best instantiated at the top level of the design and not inside a HLS IP. I think this goes along with the idea that HLS is meant to create IP's, or kernels, and not an entire system design. 

OK, I just wanted to add on to this discussion.
Scott

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dsakjl
Voyager
Voyager
741 Views
Registered: ‎07-20-2018

Hi @scampbell ,

thank you for the explanation.

I can't find RTL blackbox feature in Vitis HLS tool documentation. Will it be added in a future release?

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randyh
Xilinx Employee
Xilinx Employee
733 Views
Registered: ‎01-04-2013