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Visitor
Visitor
6,633 Views
Registered: ‎04-26-2013

Problems with UG 871 Vivado HLS Tutorial -Using HLS IP in a Zynq Processor Design

Hello

 

I'm hope i'm in the right forum.

 

So at the moment i want to do the Vivado HLS tutorial, especially this is the only tutorial who use HLS and the IP Integrator.

 

First the Lab files for "Using HLS iP in a Zynq Processor Design"  was incomplete but this probelm was solve with the last update of the files, but now i think the files are wrong
I want to archive the Lab #2 Streaming data between Zynq CPU and HLS accelerator blocks but when i go through the tutorial i get some error messages and warning messages.

 

So my first question is somewhere out there who programm successfully the tutorial?

 

The error messages are from the type BD41-66 Error running propagate TCL procdure : invalid comman name

and also i think the tutorial is wrong with the transform length of the fft block.

 

 

Kind regard

 

Achim

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Adventurer
Adventurer
6,622 Views
Registered: ‎12-23-2012

I do not have any problem on ug871. Could you provide more details?
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Visitor
Visitor
6,595 Views
Registered: ‎04-26-2013

Have you try this Lab with Zynq and the IP Integrator?

As i write in my first messages.

I think the length of the IP Blocks are wrong and

I get this strange TCL Message

BD41-66 Error running propagate TCL procdure : invalid command name

 

Achim

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Moderator
Moderator
6,586 Views
Registered: ‎04-17-2011

Are you using 2013.1 or 2013.2? This lab is supposed to be used with 2013.1 for IP Integrator flow. Did you see any error at the end of HLS IP generation (Step-1 of Lab-2)
Regards,
Debraj
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