05-07-2019 04:02 PM
I have a core that has an AXI4-Stream input and output interface. Still, the tool generates the pins ap_start, ap_done, ap_idle, ap_ready. What is the purpose of these interfaces? Should I just put a constant with value 1 connected to ap_start then perform streaming from DMA as usual into core or do I need to read the other ap signals? Are you supposed to program this ap_* interface from the processing system and use the done, idle, and ready signals?
05-14-2019 02:15 AM
Hi @johnfrye11 ,
The above-mentioned interfaces are the block level interfaces By default, they are added to the design. These signal control the block, independently with respect to any port-level I/O protocols. These ports control when the block can start processing data (ap_start), indicate when it is ready to accept new inputs (ap_ready) and indicate if the design is idle (ap_idle) or has completed operation (ap_done).
05-14-2019 03:09 AM
@johnfrye11 For a Zynq design, normally you would include this line:
#pragma HLS INTERFACE s_axilite port=return
This moves the block control ports to an AXI Lite slave, which you can plug into the Zynq PS. From here you can start the block (or set auto-restart, so it just keeps starting itself), check when it's finished, etc.
05-14-2019 08:18 AM
Does the tool still generate the ap_* interface if you use the AXI Lite to program the configs for the core? Does this interface still need to be negotiated?
How do you negotiate those signals from the PS? If you negotiate them in HW, how do negotiate them on an AXI4-Stream bus?