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Visitor vturnip
Registered: ‎06-11-2019

Read and write to off-chip memory?

The Alveo cards and many of the boards have a lot of off-chip memory. Anyone have any links of resources for how to read and write to off-chip memory using Vivado HLS? Saw someone say it involved AXI Master somehow, but wasn't able to find much beyond that.

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2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎09-05-2018

Re: Read and write to off-chip memory?

Hey @vturnip,

AXI Master is often a very good way to do this. Once you export your design to Vivado, you would connect the AXI Master port to a MIG or similar IP block. All Xilinx IP blocks have an example design you can access by right clicking and selecting Open Example Design. That's a good way to get started. I also recommend the User Guide. There's a different UG for each part: here's a link to the one for the 7-series chips: https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v1_4/ug586_7Series_MIS.pdf

Nicholas Moellers

Xilinx Worldwide Technical Support
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Scholar u4223374
Registered: ‎04-26-2015

Re: Read and write to off-chip memory?

Essentially, the off-chip memory almost always has an AXI interface. On the Zynq chips it's an AXI slave port on the PS (which then allows access to RAM through the PS memory controller). On the pure FPGAs (Spartan, Artix, Kintex, Virtex) it's an AXI slave port in the MIG block, which talks to RAM directly. To get data from an AXI slave you need an AXI master. This can either be on the HLS block (allowing that block to do random read/write in the full address space), or on a separate block that feeds the HLS block (eg. an AXI DMA, which produces an AXI stream for the HLS block to use).


Advantages of an AXI master on the block:

- Easier configuration

- Fewer resources (generally)

- Can do read/write from/to any location you want, including other AXI slaves


Advantages of a DMA feeding the block:

- AXI streams allow you to chain multiple blocks together without going back to RAM in the middle.

- DMA has a more advanced AXI master interface than HLS generates

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