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Participant eliya
Participant
1,168 Views
Registered: ‎06-21-2017

Real time dynamic functionality of the DSP block.

Hello experts,

 

I'm using vivado HLS for creating a real time IP core.

My input stream is after decimation (read the stream every 4 system clock cycle).

 

basically  'a' and 'b' are stream inputs (hls::stream) with Interval 4, which means reading the stream inputs every 4 clock cycle.
Lets say (just for the example) that I want to implement the flowing operations:
a1  = a.read;
b1  = b.read;
x1 = a1 + b1; (1st clock)
x2 = a1 - b1; (2st clock)
x3 = a1 + a1; (3st clock)
x4 = b1 + b1; (4st clock)

It is also possible to implement the whole computation on a single DSP block by using dynamic programmability to change the functionality of the DSP block on the-fly.

x1,x2,x3,x4  variables are used for more operations and not necessary dependent of each other.

If yes, I'd like to know which code needed to be implement it (code + #Pragmas)

Regard,
Eliya

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4 Replies
Xilinx Employee
Xilinx Employee
1,161 Views
Registered: ‎08-01-2008

Re: Real time dynamic functionality of the DSP block.

you can easily implement with DSP48 macro
https://www.xilinx.com/support/documentation/ip_documentation/xbip_dsp48_macro/v3_0/pg148-dsp48-macro.pdf

use select line to control DSP function
Thanks and Regards
Balkrishan
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Participant eliya
Participant
1,156 Views
Registered: ‎06-21-2017

Re: Real time dynamic functionality of the DSP block.

 

Thank you for your replay.

 

How can I use DSP48 Macro in vivado HLS?

 

Regards,

Eliya

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Xilinx Employee
Xilinx Employee
1,090 Views
Registered: ‎08-01-2008

Re: Real time dynamic functionality of the DSP block.

DSP48 macro Core you can use in vivado from IP catalog . 

Vivado HLS relies on synthesis tools such as Synplify, XST, or Vivado Synthesis to infer operation patterns such MAC or pre-adder in DSP48 primitives. The following checklist provides possible reasons for the lack of DSP48 primitives. 

  1. Constant multiplications: Constant multiplications can sometimes be implemented using shift-add-sub efficiently, and Vivado HLS may eliminated the need for a multiplication and thus a MAC.
  2. Multiplier fanout: If the result of a multiplication is used by multiple other operations, it often cannot be combined with a post-adder. Therefore, it is better if the post-adder has the fanout.
  3. Bit-widths: The bit-widths of the two operands need to fit into the DSP48. For example, 25x18 for a DSP48E/E1 and 18x18 for a DSP48A/A1 and the result should be less than 48 bits. Refer to the user guide for more information on DSP primitive for the device.(Xilinx Documentation - User Guide)
  4. Operand signs: DSP48 inputs are signed; therefore use signed data types for multiplications whenever possible.
  5. Resource assignment: If the operation is associated with CORE Generator IP core through the resource directive, the operation will be implemented as is described by the IP core.
  6. Synthesis tool preference: It is possible for the synthesis tool to avoid inferring DSP48 primitive.

After verifying the items listed in the checklist and Vivado HLS' output still doesn't result in expected DSP48 implementation, contact Xilinx technical support for additional assistance.

Thanks and Regards
Balkrishan
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Explorer
Explorer
1,085 Views
Registered: ‎08-31-2017

Re: Real time dynamic functionality of the DSP block.

@balkris

 

 What you mentioned in the thread is to instantiate the DSP48 macro code in HLS C/C++ or in RTL code ? Thanks

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