12-13-2017 06:35 AM - edited 12-13-2017 07:08 AM
I'm using vivado HLS for creating a real time IP core.
My input stream is after decimation (read the stream every 4 system clock cycle).
basically 'a' and 'b' are stream inputs (hls::stream) with Interval 4, which means reading the stream inputs every 4 clock cycle.
Lets say (just for the example) that I want to implement the flowing operations:
a1 = a.read;
b1 = b.read;
x1 = a1 + b1; (1st clock)
x2 = a1 - b1; (2st clock)
x3 = a1 + a1; (3st clock)
x4 = b1 + b1; (4st clock)
It is also possible to implement the whole computation on a single DSP block by using dynamic programmability to change the functionality of the DSP block on the-fly.
x1,x2,x3,x4 variables are used for more operations and not necessary dependent of each other.
If yes, I'd like to know which code needed to be implement it (code + #Pragmas)
12-13-2017 06:47 AM
12-13-2017 07:11 AM
12-18-2017 12:42 AM
DSP48 macro Core you can use in vivado from IP catalog .
Vivado HLS relies on synthesis tools such as Synplify, XST, or Vivado Synthesis to infer operation patterns such MAC or pre-adder in DSP48 primitives. The following checklist provides possible reasons for the lack of DSP48 primitives.
After verifying the items listed in the checklist and Vivado HLS' output still doesn't result in expected DSP48 implementation, contact Xilinx technical support for additional assistance.
12-18-2017 01:53 PM