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Adventurer
Adventurer
810 Views
Registered: ‎11-06-2017

Regarding Writing from HLS module to the DDR

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Dear All,

@scampbell 
@florentw 
@hemangd 

I have created a simple module by HLS, in order to write a set of data (50x32-bit) to the DDR. The HLS module is connected through a m_axi port to the s_axi_hp0_fpd port of the PS.
Here is the HLS code:

//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
#include <ap_int.h>
#include <string.h>
#include <stdint.h>

typedef ap_uint<32> uint32;

void axi_mem_interface_v1
(
volatile uint32 *ddr

)

{

#pragma HLS INTERFACE s_axilite port=return bundle=registers
#pragma HLS INTERFACE m_axi depth=50 port=ddr offset=slave

int i;

     for(i=0; i<50; i++){
     #pragma HLS PIPELINE
     ddr[i] = i;
      }

}

//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
this code provides a s_axi_lite access also to be connected to the m_axi_hpc0_lpd of the PS. I used following codes in SDK running standalone baremetal software, to test my module.
We have a function to start module, and another function to set the offset of the DDR access from the HLS module. Here is the code which is in a loop:



//------------------------------------------------------------------------------------------------------------------------------------------------------------------------

axi_mem_offset = 0x10 + axi_mem_offset;

XAxi_mem_interface_v1_Set_ddr_V(&AxiMemInterface, axi_mem_offset);
printf("[USER-INFO] AXI MEM OFFSET VALUE = %x\n\r",XAxi_mem_interface_v1_Get_ddr_V(&AxiMemInterface));

XAxi_mem_interface_v1_Start(&AxiMemInterface);
while(!XAxi_mem_interface_v1_IsDone(&AxiMemInterface));


printf("[USER-INFO] READING THE MEM ... \n\r");
for (i=axi_mem_offset; i<400; i=i+4)
xil_printf ("\r\n DDR READ %d (addr=0x%.8x)= 0x%x",i/4,i,Xil_In32(i));
//-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

THE PROBLEM:

for the first time when I pass the offset value from the PS to the PL, the HLS module correctly fills the FRAME into the DDR. In he above loop for the second iteration, the OFFSET value is correctly loaded into the correponsing register, however, unfortunately the HLS modules still fills the previous OFFSET and doesnt see the new updated value for the OFFSET.

Is any body faced this problem. I appreciate your given time.

Regards,
Farnam

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1 Solution

Accepted Solutions
Adventurer
Adventurer
374 Views
Registered: ‎11-06-2017

Dear All,

I was able to solve my problem, with the following snippet of my HLS module. I can write/read to/from the DDR from PL, with maximum 7 Clock Cycle Latency (reported by HLS). I connected my HLS module to the S_AXI_HP0 port of the PS.

typedef ap_uint<1> uint1;
typedef ap_uint<64> uint64;

void dma_v1.0 (
volatile uint64 *ps_mem,
uint1 addr_valid
)
{
#pragma HLS PIPELINE
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE m_axi depth=32 port=ps_mem offset=direct

if (addr_valid==1) {

ps_mem[0] = 0x5555666677778888;
ps_mem[1] = 0x1111222233334444;
ps_mem[2] = tik_time;

}

DebugA = ps_mem[3];
DebugB = ps_mem[4] ;
DebugNodeA = DebugA;
DebugNodeB = DebugB;


}

In this code, I have used a valid bit ("addr_valid") to ensure that the base address of the module (which is materialized through the pragma offset= direct), is properly chosen and set, otherwise the default address is 0x0000000 and would break the running Software (bare metal/OS)by writing there. 

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1 Reply
Adventurer
Adventurer
375 Views
Registered: ‎11-06-2017

Dear All,

I was able to solve my problem, with the following snippet of my HLS module. I can write/read to/from the DDR from PL, with maximum 7 Clock Cycle Latency (reported by HLS). I connected my HLS module to the S_AXI_HP0 port of the PS.

typedef ap_uint<1> uint1;
typedef ap_uint<64> uint64;

void dma_v1.0 (
volatile uint64 *ps_mem,
uint1 addr_valid
)
{
#pragma HLS PIPELINE
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE m_axi depth=32 port=ps_mem offset=direct

if (addr_valid==1) {

ps_mem[0] = 0x5555666677778888;
ps_mem[1] = 0x1111222233334444;
ps_mem[2] = tik_time;

}

DebugA = ps_mem[3];
DebugB = ps_mem[4] ;
DebugNodeA = DebugA;
DebugNodeB = DebugB;


}

In this code, I have used a valid bit ("addr_valid") to ensure that the base address of the module (which is materialized through the pragma offset= direct), is properly chosen and set, otherwise the default address is 0x0000000 and would break the running Software (bare metal/OS)by writing there. 

View solution in original post

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