03-28-2018 05:01 AM
I am using Vivado HLS 2017.4 to program a Zynq-7020 using a 100MHz clock (10ns). How come that some operations in 32-bit have more latency than their 64-bit counterparts?
I got these results from the performance tab in the analysis view.
03-28-2018 10:34 AM
What operations are having more latency? Are they implemented with the same type of resource? Can you show where you are seeing this difference?
Can you also show the details from the performance reports on the latency numbers you are seeing between the two?
03-28-2018 11:59 AM
as you can see in the table, 32-bit substractions and additions (fsub and fadd) have latency equal to 5, whereas their 64-bit counterparts have 4. Yes, they use less resources, but it does not make much sense to need more clock cycles to perform an operation with less bits.
They all use DSPs for it according to Vivado HLS.