cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
cerilet
Explorer
Explorer
1,416 Views
Registered: ‎08-26-2014

Resources utilisation for 32 and 64-bit operations

Hi,

 

I am using Vivado HLS 2017.4 to program a Zynq-7020 using a 100MHz clock (10ns). How come that some operations in 32-bit have more latency than their 64-bit counterparts?

 

FPGA floating-point latency resources utilisation per operation.png

 

I got these results from the performance tab in the analysis view.

 

BR,

 

Cerilet

0 Kudos
2 Replies
evant
Xilinx Employee
Xilinx Employee
1,375 Views
Registered: ‎09-08-2011

What operations are having more latency? Are they implemented with the same type of resource? Can you show where you are seeing this difference?

 

Can you also show the details from the performance reports on the latency numbers you are seeing between the two?

 

-Evan

If at first you don't succeed, try redefining success?
0 Kudos
cerilet
Explorer
Explorer
1,369 Views
Registered: ‎08-26-2014

Hi @evant,

 

as you can see in the table, 32-bit substractions and additions (fsub and fadd) have latency equal to 5, whereas their 64-bit counterparts have 4. Yes, they use less resources, but it does not make much sense to need more clock cycles to perform an operation with less bits.

 

They all use DSPs for it according to Vivado HLS.

0 Kudos