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cerilet
Explorer
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Registered: ‎08-26-2014

Results from HLS C simulation and then its hardware implementation shouldn't be equals?

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Hi,

 

I am evaluating an IP which uses 32-bit floating-point input and output variables. I have as a golden data a Simulink model using 64-bit floating-point variables. I run the Simulink model and store input and output values.

 

Then, in Vivado HLS, I read 1024 input values from the Simulink model and then ran the C simulation. The comparison between the Simulink results and this are acceptable considering the data conversion from 32- to 64-bits.

 

Then I generate an IP from that HLS code, create a Vivado project, add the IP, the stimuli (which are exactly the same I use in the HLS C simulation), and then I get this results:

 

These are the actual output values:

2017-1-18_17-47-24 outputs (blue = HLS sim, red = Zynq impl).png

And here the errors of both the HLS C simulation and the hardware implementation compared to the golden data (the simulink model):

2017-1-18_17-47-25 output errors (HLS sim - Zynq impl).png

Shouldn't the results from the C simulation and the FPGA implementation be exactly the same? In some cases they differ significantly, but we can see in the first picture that the signals follow the reference data.

 

Thanks in advance.

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u4223374
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Registered: ‎04-26-2015

Did you try running cosimulation?

 

If the cosimulation results match the C simulation results perfectly, then the problem is likely (although not certain) to be in your test code; given that the data is very close to what you expect, it could just be a rounding error from one format to another.

 

If the cosimulation results don't match the C simulation results, then that's going to be a pain in the neck to debug. My only advice there is to make sure you've got the latest HLS version; I've got one block that totally fails in 2016.2 but works in 2016.4.

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u4223374
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9,354 Views
Registered: ‎04-26-2015

Did you try running cosimulation?

 

If the cosimulation results match the C simulation results perfectly, then the problem is likely (although not certain) to be in your test code; given that the data is very close to what you expect, it could just be a rounding error from one format to another.

 

If the cosimulation results don't match the C simulation results, then that's going to be a pain in the neck to debug. My only advice there is to make sure you've got the latest HLS version; I've got one block that totally fails in 2016.2 but works in 2016.4.

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cerilet
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Registered: ‎08-26-2014

Hi @u4223374,

 

Ok, I have tried the cosimulation and verified the data. They do not differ in the same manner as they do after the implementation in the Zynq.

 

My program reads a data file and then it writes out the results to later be compared using Matlab. However, in the SIM folder there are two subfolders (WRAPC and WRAPC_PC) where I find two different output files.  What is the difference between those two subfolders?

 

Thanks for your help @u4223374.

 

Cerilet

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u4223374
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Registered: ‎04-26-2015

@cerilet

 

I'm pretty sure that one of those is the actual cosimulation result, and the other is from the C simulation that HLS automatically runs before cosimulation. Can't remember which, though - I normally just dump everything to text files in locations that I can find easily.

 

Are you now seeing three different results? One result from C simulation (matches Matlab, or close enough), one from cosimulation (doesn't match C simulation), and a third from hardware (doesn't match either C simulation or cosimulation)? If so, that's a really nasty situation to be in.

cerilet
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Registered: ‎08-26-2014
I have found that WRAPC_PC is the C simulation. The results are identical. So I guess the folder WRAPC is the cosimulation.

I repeated the tests and now they match quite well. Maybe I did something wrong in the first graphs I showed.

Thanks again for your help @u4223374!
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