SDAccel HLS Stream FIFO's hang in hardware emulation in C

[cceev]

Hi,

I'm working on a project in SDAccel that contains one kernel that sorts fifo data into a larger fifo. I am trying to use the .empty() and .full() signals of the input fifo's to read the data and input it into the output fifo. The code shown below works in software emulation, but hangs in hardware emulation. I've also tried using counters and reading the fifos that way, and that works, but requires a lot of extra logic.

I've explored the "#pragma HLS INTERFACE" attribute with no success. Does anyone know what i'm doing wrong?

void FIFO_node(	hls::stream<int> &input1,
				hls::stream<int> &input2,
				hls::stream<int> &output,
				bool sel){

		int temp;
		if(!input1.empty() && !input2.empty()){
			temp = (sel)?input1.read():input2.read();
			output.write(temp);
			sel=!sel;
		}else if(!input1.empty() && input2.empty()){
			temp = input1.read();
			output.write(temp);
		}else if(!input2.empty() && input1.empty()){
			temp = input2.read();
			output.write(temp);
		}
		return;
}

void FIFO_tree(	hls::stream<int> &in0_0,
		 	 	hls::stream<int> &in0_1,
		 	 	hls::stream<int> &in0_2,
		 	 	hls::stream<int> &in0_3,
		 	 	hls::stream<int> &in0_4,
		 	 	hls::stream<int> &in0_5,
				hls::stream<int> &output,
				int load_sum,
				int max,
				int run_row2
				){
	hls::stream<int> in1_0("in1_0");
	hls::stream<int> in1_1("in1_1");
	hls::stream<int> in1_2("in1_2");
	hls::stream<int> in2_0("in2_0");

	bool sel0=false,sel1=true,sel2=false,sel3=true,sel4=false;
	for(int i=0;i<max;i++){
		//#pragma HLS DATAFLOW
		FIFO_node(in0_0,in0_1,in1_0,sel0);
		FIFO_node(in0_2,in0_3,in1_1,sel1);
		FIFO_node(in0_4,in0_5,in1_2,sel2);
	}
	for(int i=0;i<run_row2;i++){
		FIFO_node(in1_2,in1_1,in2_0,sel3);
	}
	for(int i=0;i<load_sum;i++){
		FIFO_node(in1_0,in2_0,output,sel4);
	}
	return;
}

[wenchen]

Hi @cceev 

How is this problem going? Please provide some info about how the co-sim fails and which interface are you applying?

Thanks,

Wen

[cceev]

I have been able to get the design to work by defining the interface as 'axis' using the 'INTERFACE' attribute. This had to be done in a specific order:

static hls::stream<int> stream1;
#pragma HLS INTERFACE axis poirt=stream1
#pragma HLS STREAM variable=stream1 depth=100

Additionally, the design only worked when the kernel called one process, having streams between the one process. It wouldn't allow me to have the kernel call one process and have that process call another process within it and connect the streams. I had to limit it to one level deep.