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Explorer
Explorer
589 Views
Registered: ‎02-06-2018

SSR FFT output is not hermitian symmetric

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Hi

I am using Vivado 2019.1 (SDK and HLS) and I have implemented SSR HLS using available documentations. I feed data to a SSR FFT with following specification:

FFT Length = 1024

SSR Factor = 8

Bit Width = 16

The output I'm getting is not center symmetric and is shifted a little to right. Do you know what is causing the issue? Are there any documentation describing the output of the SSR FFT library? Like how bits are generated by the block?

Here is the graph of absolute values of an example output (sqrt(real^2 + imag^2)), as you can see, it is shifted a little to right.

Absolute.png

 

Thank you.

 

 

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Explorer
Explorer
496 Views
Registered: ‎02-06-2018

Hi,

so I finally figured out what the problem is, it was because of wrong data interpretation. Now the output is fine as below (for 600MHz signal):Absolute_600MHz.png

 When simulating, I was feeding data to FFT block in a wrong way. The second index should be time and you should pay attention how you simulate it.

 

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1 Reply
Explorer
Explorer
497 Views
Registered: ‎02-06-2018

Hi,

so I finally figured out what the problem is, it was because of wrong data interpretation. Now the output is fine as below (for 600MHz signal):Absolute_600MHz.png

 When simulating, I was feeding data to FFT block in a wrong way. The second index should be time and you should pay attention how you simulate it.

 

View solution in original post