11-10-2017 09:18 AM
I'm doing an image processing project on Zedboard Zynq evaluation board, using the FPGA built on it. I have written the image processing block using HLS and created the IP with both input and output as AXI4 streams with width 8.
How do I read a JPEG image on my PC and send it as an AXI4 stream to this IP block, and output it back to show it on my PC screen ?
Are there any existing IPs which accomplish this ?
P.S. The FPGA board is connected to my PC via JTAG cable, in case it's relevant.
11-10-2017 10:04 AM
Basically, there are example designs for various platforms to use cameras, displays, or file transfer of images.
11-12-2017 06:17 PM
I'm sorry, I couldn't find any relevant material in the link given. Could you please guide me more specifically, or ask any of your other colleagues to help me out ?
11-13-2017 02:20 AM
There's not a really good way to do this. The JTAG to AXI Master IP could potentially do what you want, but it doesn't do a stream output. You could either copy data into RAM and then use a VDMA to feed it to the HLS block, or use something like an AXI FIFO to avoid off-chip RAM (this approach will require careful timing, as you can't buffer the whole image on-chip).
I would suggest two other options:
(1) Use the UART or ethernet ports to copy data into the RAM (via the Zynq PS), then read it with a VDMA.
(2) Put the pictures on an SD card, have the Zynq PS read them from there, convert to raw, feed them to the block, then write the results back to the SD card.