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Harish_Algat
Participant
Participant
378 Views
Registered: ‎06-04-2020

Setup and hold violations

I have generated Timing Report Post synthesis and I have both setup and Hold violations. The timing summary is as follows:

No Clock: there are 228 registers/latch pins with no clock. driven by root clock pin :- dbg_hub/sl_iport0_o[1]

unconstrained internal endpoints: 298 pins that are not constrained for maximum delay

No Input delay : 3 input ports with no input delay

no output delay : 11 output ports with no output delay

 

setup and Hold violation:

setup:

WNS:-3.882ns

TNS:-38.817ns

failing endpoints : 24

hold:

WHS:-0.595ns

THS:-1696.736ns

Number of Failing Endpoints : 16656

 

 

I am a beginner and I want to understand where are I am committing mistakes. Can anyone help me sorting this out.

Thanks and Regards,

Harish Algat

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aoifem
Moderator
Moderator
332 Views
Registered: ‎11-21-2018

Hi @Harish_Algat 

I would need to see your source code before I understand exactly what you are doing wrong. 

Some tips to reduce timing might be: 

- What board are you trying to target? Newer boards such as the 7 series are a bit easier to debug. 

- Can you simplify your design and try to focus on any areas that significantly increase timing, like high fanout nets, or large carry chains? 

- Config Schedule Pragma can be used to manipulate timing. 

- Do you have any complex logic such as multipliers, many if/else statements, loops, nested loops, comparisons etc. which might increase timing? Can you replace these? 

 

There is also a forums board which is specific to timing which might be helpful: 

https://forums.xilinx.com/t5/Timing-Analysis/bd-p/TIMEANBD

 

We have a sticky post aimed at beginners to HLS that lists a lot of our source documentation and tutorials. 

https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/HLS-Key-Documents-and-Getting-Started-FAQ/td-p/1118001

The optimization guide, and the tutorials guide might be useful to read through: 

UG1270

UG871

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


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