10-27-2020 11:08 PM
I have generated Timing Report Post synthesis and I have both setup and Hold violations. The timing summary is as follows:
No Clock: there are 228 registers/latch pins with no clock. driven by root clock pin :- dbg_hub/sl_iport0_o
unconstrained internal endpoints: 298 pins that are not constrained for maximum delay
No Input delay : 3 input ports with no input delay
no output delay : 11 output ports with no output delay
setup and Hold violation:
failing endpoints : 24
Number of Failing Endpoints : 16656
I am a beginner and I want to understand where are I am committing mistakes. Can anyone help me sorting this out.
Thanks and Regards,
10-30-2020 04:55 AM - edited 10-30-2020 05:21 AM
I would need to see your source code before I understand exactly what you are doing wrong.
Some tips to reduce timing might be:
- What board are you trying to target? Newer boards such as the 7 series are a bit easier to debug.
- Can you simplify your design and try to focus on any areas that significantly increase timing, like high fanout nets, or large carry chains?
- Config Schedule Pragma can be used to manipulate timing.
- Do you have any complex logic such as multipliers, many if/else statements, loops, nested loops, comparisons etc. which might increase timing? Can you replace these?
There is also a forums board which is specific to timing which might be helpful:
We have a sticky post aimed at beginners to HLS that lists a lot of our source documentation and tutorials.
The optimization guide, and the tutorials guide might be useful to read through:
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