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Observer
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Registered: ‎09-08-2017

Simulation for Axi lite arrays in systemc

I have the following definitions in my top level systemc module:

 

sc_in<uint32_t> Reg_Channel[32];

(in the constructor)

#pragma HLS ARRAY_PARTITION variable = Reg_Channel complete dim = 1

#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=Reg_Channel

 

It compiles fine, but in cosim I am getting the following error:

DataRecorder_rtl_wrapper.h:230:28: error: 'struct ap_rtl::DataRecorder' has no member named 'Reg_Channel'; did you mean 'Reg_Channel_0'?
DataRecorder_inst->Reg_Channel(rtl_Reg_Channel);

 

Any solution for this?

Tobin

 

 

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Registered: ‎05-27-2018

回复: Simulation for Axi lite arrays in systemc

hi @tobinhall .

    Refer to UG902 page135, the dimension option can only be used when patitioning multi-dimensional arrays

    Using the block style and the factor option properly may solve this problem.

#pragma HLS array_partition variable=AB block factor=4

 

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Registered: ‎09-08-2017

回复: Simulation for Axi lite arrays in systemc

@wenchen,

Thanks for the reply.

Along with the origional I tried 

#pragma HLS ARRAY_PARTITION variable = Reg_Channel complete

and

#pragma HLS ARRAY_PARTITION variable = Reg_Channel block factor=32

All 3 pragma options compile.  the first option produces a working system, I haven't tested the other 2.  All 3 fail to compile when I attempt to run Cosim with the same error as above.

 

when I tried

#pragma HLS ARRAY_PARTITION variable = Reg_Channel block factor=4

I got:

ERROR: [SCHED 204-42] Cannot implement 'load' operation ('tmp', ...) on array 'Reg_Channel' with core 'AXI4LiteS'.

looks to me that in order to use axilite the array needs to be reduced to registers.

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Registered: ‎05-27-2018

回复: Simulation for Axi lite arrays in systemc

Hi @tobinhall ,

    The problem is probably on your systemc port definition. Refer to UG902 v2019.1 page92.

    Make sure that Reg_Channel is a port under structure SC_MODULE , grouped into the same AXI4-Lite interface slv0 , not a Variable.

sc_in<sc_uint<32> > Reg_Channel;

#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=Reg_Channel

#pragma HLS ARRAY_PARTITION variable = Reg_Channel complete

 

Thanks

Wen

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Registered: ‎09-08-2017

回复: Simulation for Axi lite arrays in systemc

@wenchen 

There are two differences that I see between your code and mine:

1. Your code does not define an array, so I believe it would work, but it Does not Address the question.

2. You appear to be using a native system-c data type in the port definition. I can try that, but it doesn’t fix any of the issues you’re talking about. My understanding is that by using Sc_in<> it is being defined as a port, My code above does that.

Thanks

Tobin

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Registered: ‎05-27-2018

回复: Simulation for Axi lite arrays in systemc

Hi @tobinhall ,

     I may have misunderstood what you meant before, now I understand。Could you provide your source code that i can recurrence your project?

Thanks

Wen

 

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Registered: ‎11-21-2018

回复: Simulation for Axi lite arrays in systemc

Hi @tobinhall 

 

Are you able to provide the source code?

If you have already found a solution, could you post it here so other users can find it in the future? 

 

Regards, 

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
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Registered: ‎09-08-2017

回复: Simulation for Axi lite arrays in systemc

I can't provide our actual code, but here's an example.

as a side note for another bug, try removing the "#pragma HLS UNROLL"  and you get another apparent cosim bug. 

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Registered: ‎09-08-2017

回复: Simulation for Axi lite arrays in systemc

@aoifem @wenchen 

Forgot to tag..

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回复: Simulation for Axi lite arrays in systemc

@aoifem @wenchen

any update?
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Registered: ‎11-21-2018

回复: Simulation for Axi lite arrays in systemc

Hi @tobinhall 

Can you please see the section UG902 v2019.2 from page 380. 

  • If the variable is declared as an array of sc_in, it will become a RAM port (see p.381):RAM_Port_sys.jpg

     

     

If random access is required, a streaming AXI4LiteS cannot be used.

 

  • If the access is sequential, the variable should be declared as sc_fifo (see p.384):RAM_Port_sys2.jpg

     

    Note that it is no longer an array.

    Please let me know if that helps. 

 

Regards, 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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回复: Simulation for Axi lite arrays in systemc

@aoifem,

Thanks for the response.

I'm not sure what your are suggesting or how it applies to my problem.  Although I would like to use complete partitioning, that's not the problem.  I cannot get cosim to work no matter how I partition it. 

By the way.   I'm actually using vivado 2018.2 which seems to compile, we have tried 2019.2, but even here we can't get it to compile.

I'll reitterate my issue here again.

My design need to:

1. Use systemc.

2. Use axi-lite for register access

3. define an array to be accessed on the axi lite port.

Complete register partitioning is preferred, but not required. (it should work either way)

I have supplied an example that illustrates my problem.  

This was a cosim problem for 2018.2 / 2018.3.  In 2019.2 it now does not even synthesize, therefore I cannot cosim.

 

thanks,

Tobin

 

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Registered: ‎11-21-2018

回复: Simulation for Axi lite arrays in systemc

Hi @tobinhall 

Thank you for your summary. I think your problem is more complicated than I was initially hoping. Let me share some of my thoughts on what I've tried so far and what I think might be the issue. 

I've taken a look at your code in detail, and ran it on 2018.3 and 2019.2. When I ran it in 2019.2 I could see the following synthesis error: 

ERROR: [SCHED 204-42] Cannot implement 'load' operation ('Example_Six_m_if_Val_17', SystemC_Example/Example.cpp:34) on array 'Six' with core 'AXI4LiteS'.

Can you confirm this is the same error you were facing?

I was able to generate the systemc directory. The generated Example.h file uses the port names at the interface. Since “Six” is an array,  the port names become:systemmc_dir.jpg

 

I have two thoughts on what might be the issue: 

1. If you need a memory interface, you will need to use ap_mem_port as explained in  UG902 v2019.2 page82): PG902_82.png

2. The problem may be an internal bug. If this is the case, it will take some more time to debug. 

 

Regards, 

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎09-08-2017

回复: Simulation for Axi lite arrays in systemc

So,

To be clear this 1 problem has morphed into 2 depending on the version of HLS used.

1. For 2019.2 that's the error I'm getting the error you describe and that is part of my problem.  This seems to be introduced in 2019 as this worked for 2018.2 or 2018.3.  So to your first question, yes, I can confirm this is one problem, but not the origional problem.

2. For 2018.3 it synthesizes, but cosim does not compile for cosim due to an appearent cosim code generator bug.  One of the generated files appears to not produce correct code in the case I provided. this was the origional question for this thread.  I cannot test this case for 2019.2 due to the fact that I can't get this far, but I suspect it's still there.  This issue was the origional cause for this thread.  At that time we had not yet tried 2019.2.

 

I think there's a possibility that these 2 issues may be related and possibly have the same root cause.

as to your #1 solution, I don't need a memory interface, I need an axi-lite interface.  The sample provided should do this.

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Registered: ‎09-08-2017

回复: Simulation for Axi lite arrays in systemc

for the "Six" variable there should be some pragmas related to that.  This should be in your code if not there already

#pragma HLS ARRAY_PARTITION variable=Six complete dim=1
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle Axilites" variable=Six

the first pragma is desired, but not required (it should work either way)

the seccond is required as it specifies an axi interface.(as in my problem statement)

 

 

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回复: Simulation for Axi lite arrays in systemc

@aoifemForgot to tag... see messages above.

 

thanks,

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Registered: ‎11-21-2018

回复: Simulation for Axi lite arrays in systemc

Hi @tobinhall 

 

The first error I got in 2018.3 was as follows: 

Example_rtl_wrapper.h: In member function ‘void Example_rtl_wrapper::initInstances(ap_rtl::Example*)’:
Example_rtl_wrapper.h:112:23: error: ‘struct ap_rtl::Example’ has no member named ‘Six’; did you mean ‘Six_0’?
Example_inst->Six(rtl_Six);

Because the errors in 2018.3 and 2019.2 both relate to 'Six' I also think they are probably related.

I will need to discuss this issue internally with development to try and find the cause. However, due to the Thanksgiving holiday my response might be delayed. I will update you again as soon as I can. 

Regards,  

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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回复: Simulation for Axi lite arrays in systemc

Hi @tobinhall 

Sorry I missed your second comment on this post. 

I don't think your code included the pragmas you mentioned. Just to be clear, where exactly in the code did you add them? 

Regards, 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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回复: Simulation for Axi lite arrays in systemc

@aoifem,

Yes, that's the origional problem, so you should be able to replicate both issues.

 

Happy Thanksgiving,

Tobin.

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回复: Simulation for Axi lite arrays in systemc

@aoifem 

It's in the constructor in the header, example.h

here is a selection of that code.  

in this case ARRAYTEST is defined

	void MainLoop();
	void DelayCycle();
	SC_CTOR(Example)
	: clk("clock")
	, Reg_One("Reg_One")
	, Two("Reg_Two")
	, Reg_Three("Three")
	, Four("Four")
	, Stream_in("Stream_in")
	, Stream_out("Stream_Out")
	, internal1(0.0f)
	, internal2(false)
	{
#pragma HLS INTERFACE ap_none port = Five
#pragma HLS resource core=AXI4Stream variable=Stream_in
#pragma HLS resource core=AXI4Stream variable=Stream_out
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle Axilites" variable=Reg_One
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle Axilites" variable=Reg_Three
#ifdef ARRAYTEST
	#pragma HLS ARRAY_PARTITION variable=Six complete dim=1
	#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle Axilites" variable=Six
#endif

		//Process Registration
		SC_CTHREAD(MainLoop,clk.pos());
		reset_signal_is(reset,true);
	}
};
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回复: Simulation for Axi lite arrays in systemc

Hi @tobinhall 

 

We're still working on this internally, and hope to have an answer for you soon. 

 

Regards, 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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回复: Simulation for Axi lite arrays in systemc

Hi @aoifem

 

Are there any updates on a potential solution?
I am working on a related task that also suffers from this issue.

Thanks,

Emma

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回复: Simulation for Axi lite arrays in systemc

Hi @aoifem @wenchen,

Any progress on this.  It's been quite some time now.

Tobin 

 

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回复: Simulation for Axi lite arrays in systemc

Hi @tobinhall 

Sorry for the delay. This issue is still being investigated. I will update you with any progress as soon as I can. 

Regards, 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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回复: Simulation for Axi lite arrays in systemc

Hi @tobinhall 

Thank you again for the information you sent to me privately. 

As discussed, this was a difficult issue to debug, but I think the most likely solution is as follows: 

When C synthesis is run on the attached testcase, the following warning is shown:

WARNING: [HLS 200-41] Resource core 'AXI4LiteS' on port '&Reg_One' is deprecated. Please use the interface directive to specify the AXI interface.

It seems that despite the deprecated warning , the Axi Lite adapter is indeed instantiated. I have a working example that shows this, but is unfortunitely too big to post on the forums. If you would like a copy of the example please let me know and I can email it privately. 

 

> cat README.txt

--

  1. Modified the original customer testcase a little bit to run without ARRAYTEST defined.
  2. vivado_hls hem.tcl : Ran with current 2020.1 nightly.
  3. Check the component.xml. It has the usage of the specified bundle: AxiliteS wrapper.

More notes:

  1. It works as documented in the ug902, inspite of the deprecated warning.
  2. ug902 says (page 93, where this usage is documented):

    - When the SystemC design is synthesized, it results in an RTL design with standard RTL ports.   

   - When the design is packaged as IP using "Export RTL", the output is a design with an AXI4-Lite interface.

  1. Point 2 above is why I looked into component.xml (output of export_design) to verify the bundle creation.

 

In 2018.3 the case synthesizes ok, but fails during CoSim due to the following errors:
Example_rtl_wrapper.h: In member function ‘void Example_rtl_wrapper::initInstances(ap_rtl::Example*)’:
Example_rtl_wrapper.h:112:23: error: ‘struct ap_rtl::Example’ has no member named ‘Six’; did you mean ‘Six_0’?
Example_inst->Six(rtl_Six);

In 2019.2 the testcase fails during synthesis due to the following errors:
ERROR: [SCHED 204-42] Cannot implement 'load' operation ('Example_Six_m_if_Val_17', SystemC_Example/Example.cpp:34) on array 'Six' with core 'AXI4LiteS'.;

This seems to be a SystemC construct issue. My knowledge of SystemC is limited, but I had encountered a similar issue in C++ designs. The SC_CTOR is a SystemC construct. In the constructor you need to initialize the "Six[10]" array. However, how it is initialized it is not related to HLS.  

Unfortunately, our ug-902 has no testcase that initializes a SystemC array in the constructor, but on google I have seen a for-loop being used:

https://stackoverflow.com/questions/35425052/how-to-initialize-a-systemc-port-name-which-is-an-array

 

Regards, 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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