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846 Views
Registered: ‎11-05-2018

Strange behavior of C/RTL cosimulation

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I tried the following program with Vivado HLS 2018.2 in Windows 10 which copies a 16bit packed integer stream to an unpacked integer stream.

 

#include <ap_int.h>
#include <hls_stream.h>
#include <stdint.h>

void copy_ib2(int32_t w, int32_t h, hls::stream<ap_uint<16> > & in, hls::stream<uint8_t> & out)
{
#pragma HLS interface s_axilite port=h bundle=BUS_AXI4LS
#pragma HLS interface s_axilite port=w bundle=BUS_AXI4LS
#pragma HLS interface axis port=in
#pragma HLS interface axis port=out
ap_uint<16> bv;

for (int32_t i = 0; i < w * h; i++) {
int32_t x = i % w;
#pragma HLS pipeline II=1
if (i % 2 == 0) {
bv = in.read();
}
int32_t li = x % 2;
uint8_t v = bv.range((li + 1) * 8 - 1, li * 8);
out.write(v);
}
return;
}

 

 

#include <cstdio>
#include <ap_int.h>
#include <hls_stream.h>
#include <stdint.h>

void copy_ib2(int32_t w, int32_t h, hls::stream<ap_uint<16> > & in, hls::stream<uint8_t> & out);

int main(int argc, char *argv[])
{
hls::stream<ap_uint<16> > in;
hls::stream<uint8_t> out;

int32_t w = 6, h = 2;
for (int32_t i = 0; i < w * h; i+=2) {
ap_uint<16> b;
b.range(7, 0) = i;
b.range(15, 8) = i + 1;
in.write(b);
}
copy_ib2(w, h, in, out);
bool success = true;
for (int32_t i = 0; i < w * h; i++) {
uint8_t r = out.read();
if (r != i) {
printf("expects %d, actual %d\n", i, r);
success = false;
}
}
if (success) {
printf("Success!!\n");
return 0;
} else {
return 1;
}
}

 

 

It passes C-simulation, but does not pass C/RTL cosimulation.

The following is the result of C/RTL cosimulation.

```

...

INFO: [Common 17-206] Exiting xsim at Wed Nov 7 17:10:12 2018...
INFO: [COSIM 212-316] Starting C post checking ...

expects 1, actual 0
expects 3, actual 2
expects 5, actual 4
expects 7, actual 6
expects 8, actual 9
expects 9, actual 8
expects 10, actual 11
ERROR: [COSIM 212-361] C TB post check failed, nonzero return value '1'.

...

```

When I change ``w'' at declaration of ``x'' to a constant 6, it passes both C and C/RTL cosimulation.

Is this a bug of Vivado HLS?

 

Thank you in advance for your help.

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1 Solution

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Teacher xilinxacct
Teacher
635 Views
Registered: ‎10-23-2018

Re: Strange behavior of C/RTL cosimulation

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@izumi.asakura

Remove the 'pipeline' pragma and it will work. (I think the interaction of the pipeline and the mod are not as you want)

Hope that helps

If so, please mark as solution accepted. Kudos also welcomed. :-)

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5 Replies
Highlighted
Teacher xilinxacct
Teacher
636 Views
Registered: ‎10-23-2018

Re: Strange behavior of C/RTL cosimulation

Jump to solution

@izumi.asakura

Remove the 'pipeline' pragma and it will work. (I think the interaction of the pipeline and the mod are not as you want)

Hope that helps

If so, please mark as solution accepted. Kudos also welcomed. :-)

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Visitor dong_group
Visitor
457 Views
Registered: ‎03-18-2019

Re: Strange behavior of C/RTL cosimulation

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Hello, recently I also meet with the same problem,my HLS project  also passed C-simulation, but did not pass C/RTL cosimulation. Did you resolved this problem? Could you please share the solution with me?

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312 Views
Registered: ‎11-05-2018

Re: Strange behavior of C/RTL cosimulation

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@xilinxacct 

Thank you for your help and sorry for late reply.

 

As you mentioned, I also guess that the problem is due to the bad interaction of the pipeline pragma and mod op (I'd apprerciate it if you give any documentation about that.) Actually, I solved the problem by avoiding mod because I don't want to give up pipeline.

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300 Views
Registered: ‎11-05-2018

Re: Strange behavior of C/RTL cosimulation

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@dong_group 

Sorry for the late reply.

I fixed the problem by avoiding mod in pipeline loops. As @xilinxacct mentioned, we should not use mod inside pipeline loops.

I hope this will help you.

 

Moderator
Moderator
242 Views
Registered: ‎11-21-2018

Re: Strange behavior of C/RTL cosimulation

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Hi @izumi.asakura 

 

Thank you for updating us with your solution. 

Could you mark your answer as accepted so that other users can find it quickly in the future? 

 

Regards, 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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