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mrelko
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Registered: ‎05-10-2013

Switch Statement not working correctly in HLS

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I followed some tutorials on how to use HLS and generate blocks for Vivado and the Zynq ZC702 board.  I got it to work great with simple math statements and loops, however any time I try and use a Switch Statement or try to to the equivelent If-Else statement, the result the PL gives is incorrect.  

 

Here is my test bench results from the HLS,
PASS! 21 = 21
PASS! 22 = 22
PASS! 23 = 23
PASS! 42 = 42
PASS! 42 = 42

 

This means that the .c file and the .c test bench give the same, correct, results (as expected). In the first Pass, it goes into case 1 successfully, in the second pass it goes into case 2, ect.


In moving to the SDK, I do a similar thing. I run the code on the processor, to compare it to what the FPGA is doing (Should give same result).

One of the function variables directly controls which case to run in the switch statement. I have the FPGA return this variable at the end of running, to confirm that it gets the correct data, and it does.  For some reason though, the FPGA always runs the default case, completely ignoring the fact it is told to run case 2.  

 

HLS Function Prototype:
void switcher(int inone, int intwo, int *res, int *actual)

 

OUTPUT from SDK terminal:
//T1 and T2 are passed to the FPGA (I have the FPGA return the values and then I print them to verify that it received them correctly, in this case it appears to)
//T1 tells which case to run (case 2)
//T2 is a number which doesn't do anything right now (1)
Program to test communication and time with custom block in PL
T1: 2; T2: 1
HLS peripheral is ready. Starting... Detected HLS peripheral complete. Result received.
//After the FPGA is finished running I have it return the case it was told to run (this is 'inone' in the code)
2
//21 means the FPGA ran case 1, 41 means the processor correctly ran the default case (They should both be 22)
Result from HW: 41; Result from SW: 22

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mrelko
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Registered: ‎05-10-2013

Found the solution.  There is an sp_start port that was not shown on the pinout diagram that it shows in the vhdl code.  I had to force it high, or force the return bus to be ap_none  for it to work. Tricky stuff. 

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mrelko
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Registered: ‎05-10-2013

The last 2 lines of my post were wrong,

 

Corrected:


//22 means the PS correctly ran case 2 , 42 means the PL (FPGA) incorrectly ran the default case when it was told to run case 2  (They should both be 22)
Result from HW: 42; Result from SW: 22

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mrelko
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12,146 Views
Registered: ‎05-10-2013

Found the solution.  There is an sp_start port that was not shown on the pinout diagram that it shows in the vhdl code.  I had to force it high, or force the return bus to be ap_none  for it to work. Tricky stuff. 

View solution in original post

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