Synthesis error in Vivado HLS: Abnormal program termination (11).

[jisu]

Hi all.

I have a question about synthesis in vivado HLS.

I sometimes see the error message:
Abnormal program termination (11)
Please check '/home/.../hs_err_pid***.log' for details.

When I search about this situation in google and xilinx forum, almost experts advice that see the website http://www.xilinx.com/support/answers/55854.html .

I could realize that the reasons for this error are very various.

But in my case, when I run synthesis with same project, sometimes run synthesis is successful and sometimes run synthesis fails.

This is because of complexity of hardware?

I mean, does this kind of error occur if Vivado hls cannot synthesis complex hardware?

I will explain with another example.

Let's assume that there is a project that is already synthesised successfully.

When I add the pragma such as "#pragma HLS RESOURCE variable=array_name core=FMul_fulldsp", the same error is always occured.

In this pragma, "array_name" is used like "array_name[i] = a * b;".

I did nothing without addition only one pragma, but the synthesis always failed with same error.

Overall, I think this error is occured because of haedware complexity.

Or, due to a lack of resources on the board?

Ah, I run projects on the version of Vivado 2018.3 and 2018.2.

Please any advice for me.
I will wait for your reply.

Thank you^^.

[shameera]

Hi @jisu ,

Generally, the tool should not crash. But as in your scenario just adding a pragma is making HLS to crash while synthesizing, Can you please share your project to reproduce the crash at our end, which would help us to debug further ?

[jisu · Accepted solution]

Thank you for your reply, @shameera.

I solved this problem by adding DRAM of my hos PC.
After change the size of DRAM from 16GB to 32GB, the synthesis worked without any errors.

Thank you^^