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lmaxeniro
Explorer
Explorer
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Registered: ‎09-09-2019

Synthesis passed but Co-Sim failed on hls stream interface

Hi my design currently pass the Synthesis but failed on Co-Sim stage, the error is reported as below:

 

 

.../solution1/sim/verilog/AESL_axi_master_gmem.v: Read request address 16 exceed AXI master gmem array depth: 2
$finish called at time : 559450 ps : File ".../solution1/sim/verilog/AESL_axi_master_gmem.v" Line 697
## quit
INFO: [Common 17-206] Exiting xsim at Wed May 26 14:42:56 2021...
ERROR: [COSIM 212-303] Aborting co-simulation: RTL simulation failed.  
ERROR: [COSIM 212-344] Rtl simulation failed.
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***

 

 

in log some earlier time warning -- I don't know if this matters to the stream port depth, BTW where can I set up AXI master depth value?

 

WARNING: [COSIM 212-369] AXI_master port 'host_in' has a depth of '1'. Insufficient depth may result in simulation mismatch or freeze.
WARNING: [COSIM 212-369] AXI_master port 'out2host' has a depth of '1'. Insufficient depth may result in simulation mismatch or freeze.

 

I searched around this likely the wrong setup on the stream interface (AXI port depth setup) but after updating the depth that still fails nothing improved.

Below is my interface setup, can you please help to check what might be the problem?

 

 

static const unsigned int in_buf   = 44;   
static const unsigned int out_buf  = 5;    

extern "C" {
void s256k1_krl(unsigned int *host_in, unsigned int *out2host, unsigned int num) {
#pragma HLS INTERFACE m_axi port = host_in  bundle = gmem	 //input pointer
#pragma HLS INTERFACE m_axi port = out2host bundle = gmem    //output pointer

#pragma HLS INTERFACE s_axilite port = num  bundle = control
static hls::stream<unsigned int> inStream("input_stream");
static hls::stream<unsigned int> outStream("output_stream");

#pragma HLS stream variable = inStream  depth = in_buf*16
#pragma HLS STREAM variable = outStream depth = out_buf*16

#pragma HLS dataflow
    reader(host_in, inStream, num);
    compute(inStream, outStream, num);
    writer(out2host, outStream, num);
}
}

 

 

 

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3 Replies
lmaxeniro
Explorer
Explorer
364 Views
Registered: ‎09-09-2019

Update1:

if I comment out these three lines, there will be no above error report and the Co_Sim will be able to run forward, however, after the RTL simulation, the C post checking will be fail (C test bench test before RTL simulation will be pass).

I guess it could be due to that my test bench actually feed the test vector from the axi port, without the AXI port configuration (i.e. below three lines of code) my test bench will not work?

 

 

//#pragma HLS INTERFACE m_axi port = host_in  bundle = gmem	 //input pointer
//#pragma HLS INTERFACE m_axi port = out2host bundle = gmem    //output pointer
//#pragma HLS INTERFACE s_axilite port = num  bundle = control

 

 

 

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lmaxeniro
Explorer
Explorer
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Registered: ‎09-09-2019

 

Update2, I find a solution but just don't know why is that.

my tips (though don't know why):

I can set axi port depth and the stream depth, but both of them must be aligned with my test bench setup--I mean if I managed to send in 16 test vector in TB (num=16), the interface m_axi depth and the internal stream port depth must be assigned to be same as num, otherwise, co-sim will fail.

But that raises another question, these depth values have to be fixed for a design, but the num is a variable value, so how can I deal with that in a real application?

Also I have few axi relevant questions, post in another thread(https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/question-regarding-HLS-m-axi-and-s-axilite-configuration/td-p/1246381 )--hope someone can help.. 

#pragma HLS INTERFACE m_axi port = host_in  offset=slave depth=depth_cof*in_buf  bundle=gmem	 //input pointer
#pragma HLS INTERFACE m_axi port = out2host offset=slave depth=depth_cof*out_buf bundle=gmem     //output pointer
#pragma HLS INTERFACE s_axilite port = host_in  bundle = control
#pragma HLS INTERFACE s_axilite port = out2host bundle = control

#pragma HLS INTERFACE s_axilite port = num  bundle = control
static hls::stream<IN_t>  inStream("input_stream");
static hls::stream<OUT_t> outStream("output_stream");

#pragma HLS stream variable = inStream  depth = depth_cof
#pragma HLS STREAM variable = outStream depth = depth_cof

 

 

wenchen
Moderator
Moderator
263 Views
Registered: ‎05-27-2018

Hi @lmaxeniro ,

Thanks for sharing your workaround. Yes, the interface m_axi depth and the internal stream port depth must be assigned to be the same as num.

Take the Vitis vision examples as a reference to think about how to set the m_axi depth.

Define some macro in the head file and change the parameters to config the depth.

https://github.com/Xilinx/Vitis_Libraries/blob/master/vision/L1/examples/resize/xf_resize_accel.cpp

 

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