UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply

[SystemC] AXI bus master timing

Accepted Solution Solved
Highlighted
Adventurer
Posts: 66
Registered: ‎05-12-2017
Accepted Solution

[SystemC] AXI bus master timing

I'm writing AXI bus master protocol as I'd like to access SoC RAM on Zybo board. However I'm not quite sure how to understend the interface of AXI4M_bus_port - the read methods seems to 'immediately' return values (there is no valid field exposed) while write buffers don't seem to be busy as well. Does those methods automatically wait or am I missing something?


Accepted Solutions
Adventurer
Posts: 66
Registered: ‎05-12-2017

Re: [SystemC] AXI bus master timing

Looking at the generated VHDL and timings - I need to create a FIFO between those two if I want to use AXI4M_bus_port which can stall on writes.

View solution in original post


All Replies
Teacher
Posts: 5,130
Registered: ‎03-31-2012

Re: [SystemC] AXI bus master timing

@mpiechotka your description is not very clear. What do you mean by "the read methods seems to 'immediately' return values (there is no valid field exposed)"? On its face, this behavior doesn't describe axi functionality. There should be valid field on the axi read channel.

If you are talking about your SystemC description, you shouldn't need any of these. Both read and writes should be blocking and the underlying behavior of the generated RTL should enforce the valid/ready signals and at systemC level you just observe that the read/write took some finite time to execute very similar to how processors execute your code.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Adventurer
Posts: 66
Registered: ‎05-12-2017

Re: [SystemC] AXI bus master timing

@muzaffer "On its face, this behavior doesn't describe axi functionality" - yes, that was source of my confusion as at least FIFO (which has similar problem) exposes nonblocking read/write.

So in order to write multiple values concurrently without waiting for confirmation (or pipeline multiple reads) from slave I need to have multiple CTHREADs - is that correct?
Adventurer
Posts: 66
Registered: ‎05-12-2017

Re: [SystemC] AXI bus master timing

@muzaffer Also is access to port synchronized accross threads or do I need to synchronize it as well (I presume you can issue a second read/write in following clock cycle).
Teacher
Posts: 5,130
Registered: ‎03-31-2012

Re: [SystemC] AXI bus master timing

@mpiechotka I don't have any experience with systemC usage under HLS. I write all my axi master code in C++. Normally you don't need anything complicated to get pipelined accesses. If you generate a read/write of bursts, it gets converted to axi transactions properly. I am not sure if HLS supports any form of threading. I don't think C++ synthesis supports multiple-accesses to the same maxi port but I don't know if SC supports that concept.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Adventurer
Posts: 66
Registered: ‎05-12-2017

Re: [SystemC] AXI bus master timing

@muzaffer - SystemC is much closer to VHDL/Verilog in many aspects as far as I understand so I don't think answers from 'standard' C++ works...
Teacher
Posts: 5,130
Registered: ‎03-31-2012

Re: [SystemC] AXI bus master timing

[ Edited ]

@mpiechotka in that case you have to understand that there is no way to synthesize cthreads to RTL. you have to forward all the requests to a single axi master and let it generate the actual transactions there. It's highly unlikely that cthreads in systemc are synthesizable through HLS.

 

PLEASE IGNORE THIS RESPONSE

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Adventurer
Posts: 66
Registered: ‎05-12-2017

Re: [SystemC] AXI bus master timing

@muzaffer "in that case you have to understand that there is no way to synthesize cthreads to RTL" - what do you mean? SystemC is one of the languages supported by the HLS.
Adventurer
Posts: 66
Registered: ‎05-12-2017

Re: [SystemC] AXI bus master timing

Looking at the generated VHDL and timings - I need to create a FIFO between those two if I want to use AXI4M_bus_port which can stall on writes.