05-18-2017 02:54 AM
I'm writing AXI bus master protocol as I'd like to access SoC RAM on Zybo board. However I'm not quite sure how to understend the interface of AXI4M_bus_port - the read methods seems to 'immediately' return values (there is no valid field exposed) while write buffers don't seem to be busy as well. Does those methods automatically wait or am I missing something?
05-19-2017 11:18 AM
05-18-2017 01:45 PM
@mpiechotka your description is not very clear. What do you mean by "the read methods seems to 'immediately' return values (there is no valid field exposed)"? On its face, this behavior doesn't describe axi functionality. There should be valid field on the axi read channel.
If you are talking about your SystemC description, you shouldn't need any of these. Both read and writes should be blocking and the underlying behavior of the generated RTL should enforce the valid/ready signals and at systemC level you just observe that the read/write took some finite time to execute very similar to how processors execute your code.
05-18-2017 02:47 PM
05-18-2017 03:22 PM
05-18-2017 04:55 PM
@mpiechotka I don't have any experience with systemC usage under HLS. I write all my axi master code in C++. Normally you don't need anything complicated to get pipelined accesses. If you generate a read/write of bursts, it gets converted to axi transactions properly. I am not sure if HLS supports any form of threading. I don't think C++ synthesis supports multiple-accesses to the same maxi port but I don't know if SC supports that concept.
05-18-2017 05:43 PM
05-18-2017 05:46 PM - edited 05-19-2017 10:06 AM
@mpiechotka in that case you have to understand that there is no way to synthesize cthreads to RTL. you have to forward all the requests to a single axi master and let it generate the actual transactions there. It's highly unlikely that cthreads in systemc are synthesizable through HLS.
PLEASE IGNORE THIS RESPONSE
05-18-2017 10:11 PM
05-19-2017 11:18 AM