09-26-2019 11:20 AM
It there any way to control the reset behavior of a input signal from a axilite register when using Systemc? The normal reset behavior pragmas and commands (config_rtl) don't appear to work for this. Being the the register is a sc_in, I'm not sure that I can actually control this from Systemc. Here are the 2 relevant pragmas I'm using.
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle Axilites" variable=Reg_Start #pragma HLS RESET variable=Reg_Start
the generated Verilog axilite wrapper shows no reset.
// _Reg_Start[0:0] always @(posedge ACLK) begin if (w_hs && waddr == ADDR_REG_START_DATA_0) _Reg_Start[0:0] <= (WDATA[31:0] & wmask) | (_Reg_Start[0:0] & ~wmask); end
10-03-2019 11:29 PM
Hi @tobinhall ,
Are you looking to change the polarity of the reset ?
If so, When AXI4 interfaces are used on a design the reset polarity is automatically changed to active Low irrespective of the setting in the config_rtl configuration, because this is required by the AXI4 standard.
10-04-2019 09:41 AM
No, I just wanted _reg_start (which is autogenerated by HLS) to have a known value after reset. Aside from being good practice, this issue is tripping up my simulator. I would be happy to change my reset polarity if needed, and I have done so with other designs, however in my experience that can also cause problems Particularly with fifos in systemc. It seems that fifos in my experience assume an active hi reset reguardless of what the directives and commands indicate, but that is a side issue. For this problem it's not about the polarity of reset it's what the reset is doing. Inside the design it seems to mostly work, but when the AXI wrapper is put on, the wrapper does not seem to apply the resets to registers such as _reg_start