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3,211 Views
Registered: ‎12-21-2016

SystemC sc_fifo and hierarchy

Hi,

 

I have a SC_MODULE (A) which includes a sc_fifo (written in a SC_CTHREAD and read in another SC_CTHREAD).

This SC_MODULE (A) synthesizes correctly, but when I instantiate it in another SC_MODULE (B), I get an error :

 

ERROR: [SYNCHK 200-91] Port 'x.x.Val' (x:43) of function 'x' cannot be set to a FIFO
ERROR: [SYNCHK 200-91] as it has both write (x.cpp:29:13) and read (x.cpp:104:22) operations.

 

Anyone knows if hierarchy is supported in vivado HLS with SystemC designs ?

Thanks.

 

Regards,

Mathieu

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Xilinx Employee
Xilinx Employee
3,181 Views
Registered: ‎08-01-2008

Re: SystemC sc_fifo and hierarchy

check this document . It may help you
https://www.xilinx.com/Attachment/SystemCVerif_ApNote_4.pdf
Thanks and Regards
Balkrishan
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3,170 Views
Registered: ‎12-21-2016

Re: SystemC sc_fifo and hierarchy

Thanks interesting document for mixed languages simulation in modelsim.

 

But in fact, my errors occurred during Vivado HLS systemc synthesis.

SystemC compilation with g++ and execution worked well.

 

Regards,

Mathieu

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132 Views
Registered: ‎12-16-2019

Re: SystemC sc_fifo and hierarchy

 Hello sir,

     I got the same error in my design when using sc_fifo, did you solved it?  if yes, please do help me.

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