01-05-2017 10:14 AM
I have a SC_MODULE (A) which includes a sc_fifo (written in a SC_CTHREAD and read in another SC_CTHREAD).
This SC_MODULE (A) synthesizes correctly, but when I instantiate it in another SC_MODULE (B), I get an error :
ERROR: [SYNCHK 200-91] Port 'x.x.Val' (x:43) of function 'x' cannot be set to a FIFO
ERROR: [SYNCHK 200-91] as it has both write (x.cpp:29:13) and read (x.cpp:104:22) operations.
Anyone knows if hierarchy is supported in vivado HLS with SystemC designs ?
01-05-2017 09:26 PM
01-06-2017 02:32 AM
Thanks interesting document for mixed languages simulation in modelsim.
But in fact, my errors occurred during Vivado HLS systemc synthesis.
SystemC compilation with g++ and execution worked well.