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Registered: ‎05-01-2018

The problems when exporting RTL with hls::fft

I am using the hls::fft to implement 2d FFT in image procesing ,but when i trying to exporting RTL  in vivado hls,i met some problems is given below,I don't know how to deal with it ,if you have some ideas please contact me ,thank you in advance !

ERROR: [Synth 8-448] named port connection 'xn_address0' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:596]
ERROR: [Synth 8-448] named port connection 'xn_ce0' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:597]
ERROR: [Synth 8-448] named port connection 'xn_we0' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:598]
ERROR: [Synth 8-448] named port connection 'xn_d0' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:599]
ERROR: [Synth 8-448] named port connection 'xn_q0' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:600]
ERROR: [Synth 8-448] named port connection 'xn_address1' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:601]
ERROR: [Synth 8-448] named port connection 'xn_ce1' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:602]
ERROR: [Synth 8-448] named port connection 'xn_we1' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:603]
ERROR: [Synth 8-448] named port connection 'xn_d1' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:604]
ERROR: [Synth 8-448] named port connection 'xn_q1' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:605]
ERROR: [Synth 8-448] named port connection 'xk_address0' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:606]
ERROR: [Synth 8-448] named port connection 'xk_ce0' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:607]
ERROR: [Synth 8-448] named port connection 'xk_we0' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:608]
ERROR: [Synth 8-448] named port connection 'xk_d0' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:609]
ERROR: [Synth 8-448] named port connection 'xk_q0' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:610]
ERROR: [Synth 8-448] named port connection 'xk_address1' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:611]
ERROR: [Synth 8-448] named port connection 'xk_ce1' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:612]
ERROR: [Synth 8-448] named port connection 'xk_we1' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:613]
ERROR: [Synth 8-448] named port connection 'xk_d1' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:614]
ERROR: [Synth 8-448] named port connection 'xk_q1' does not exist for instance 'grp_fft_config1_s_fu_331' of module 'fft_config1_s' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:615]
INFO: [Synth 8-638] synthesizing module 'array_fft_sitofp_bkb' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/array_fft_sitofp_bkb.v:11]
ERROR: [Synth 8-285] failed synthesizing module 'array_fft_sitofp_bkb' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/array_fft_sitofp_bkb.v:11]
ERROR: [Synth 8-285] failed synthesizing module 'FF' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/FF.v:10]
ERROR: [Synth 8-285] failed synthesizing module 'img_fft46' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/img_fft46.v:10]
ERROR: [Synth 8-285] failed synthesizing module 'array_fft' [C:/Users/MN/Desktop/AXI_FFT_15_2INPUT/AXI_FFT_15_2INPUT/AXI_FFT_15/solution1/impl/verilog/array_fft.v:12]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:07:06 ; elapsed = 00:07:51 . Memory (MB): peak = 658.660 ; gain = 448.547
---------------------------------------------------------------------------------
RTL Elaboration failed

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Visitor zinnc
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Registered: ‎08-06-2014

Re: The problems when exporting RTL with hls::fft

same here.

In C++ code, we write a simple cross correlation:

 

void cross_correlation (cmpxData * a,cmpxData * b,cmpxData * c)
{
	hls::Mat<TMP_ROWS,TMP_COLS,HLS_32F> img_(TMP_ROWS,TMP_COLS);
	cmpxData a_out[FFT_LENGTH];
	cmpxData b_out[FFT_LENGTH];
	float real_mul_ab_re;
	float real_mul_ab_im;

    config_t fft_config_a;
    status_t fft_status_a;
    fft_config_a.setDir(1);  //FWD

    config_t fft_config_b;
    status_t fft_status_b;
    fft_config_b.setDir(1);			

#pragma HLS dataflow
    //fft_config_a.setSch(0x2AB);
    hls::fft<config1>(a, a_out, &fft_status_a, &fft_config_a);


    //fft_config_b.setSch(0x2AB);
    hls::fft<config1>(b, b_out, &fft_status_b, &fft_config_b);

    for(int i=0;i<TMP_LENGTH;i++)
    {
#pragma HLS pipeline
    	//a*cnj_b
    	real_mul_ab_re = a_out[i].real() * b_out[i].real() + a_out[i].imag()*b_out[i].imag();
    	real_mul_ab_im = a_out[i].imag() * b_out[i].real() - a_out[i].real()*b_out[i].imag();
    	c[i] = cmpxData(real_mul_ab_re,real_mul_ab_im);
    }
}

 

But in verilog, it turns as

 

fft_config1_s fft_config1_U0(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(fft_config1_U0_ap_start),
    .ap_ce(1'b1),
    .ap_done(fft_config1_U0_ap_done),
    .ap_idle(fft_config1_U0_ap_idle),
    .ap_ready(fft_config1_U0_ap_ready),
    .ap_continue(fft_config1_U0_ap_continue),
    .xn_address0(fft_config1_U0_xn_address0),
    .xn_ce0(fft_config1_U0_xn_ce0),
    .xn_we0(fft_config1_U0_xn_we0),
    .xn_d0(fft_config1_U0_xn_d0),
    .xn_q0(64'd0),
    .xn_address1(fft_config1_U0_xn_address1),
    .xn_ce1(fft_config1_U0_xn_ce1),
    .xn_we1(fft_config1_U0_xn_we1),
    .xn_d1(fft_config1_U0_xn_d1),
    .xn_q1(64'd0),
    .xk_din(fft_config1_U0_xk_din),
    .xk_full_n(a_out_channel_full_n),
    .xk_write(fft_config1_U0_xk_write),
    .status_data_V_din(fft_config1_U0_status_data_V_din),
    .status_data_V_full_n(1'b1),
    .status_data_V_write(fft_config1_U0_status_data_V_write),
    .config_ch_data_V_dout(fft_config_a_data_V_s_dout),
    .config_ch_data_V_empty_n(fft_config_a_data_V_s_empty_n),
    .config_ch_data_V_read(fft_config1_U0_config_ch_data_V_read)
);

 both fft_config1_U0_xn_d0 and fft_config1_U0_xn_d1 link to wires which connect to no where.

When we put the IP into Vivado, we have :

named port connection 'xn_address0' does not exist for instance 'fft_config1_U0' of module 'fft_config1_s' 

 

Can someone help?

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