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KKilic
Observer
Observer
673 Views
Registered: ‎01-01-2021

Timing Violation in simple protocol parser

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Hi,

I am trying to write a network protocol parser. I read all documents and I'm trying to follow all the recommendations but still I get timing violation. Any help is appreciated.

Variables:

	transPkt currRead;
	ap_uint<8> localMessageType;

	static ap_uint<11> currentMessageLength;
	static ap_uint<11> currentMessageOffset;
	static ap_uint<8> currentMessageType;
	static ap_uint<8> previoudHeaderFirst;
	static writePkt writeBuffer;

and my state code:

		case S_INHEADER1:

			if (! input.empty()){

				input.read(currRead);

				localMessageType = currRead.data.range(15, 8);

				if (localMessageType == 84/*T*/) {
						currentMessageLength = (currRead.data.range(55, 48),currRead.data.range(63, 56) ) * 8 ;
						currentMessageOffset=0;
						mState = S_IN_ZERO;
				}
				else {
					currentMessageLength =  (previoudHeaderFirst.range(7, 0),currRead.data.range(7, 0) ) * 8 ;   // 1 Bytes Header
					currentMessageType = localMessageType;
					writeBuffer.data.range(7,0) = localMessageType; // 1 Byte Message Type
					writeBuffer.data.range(24,8) = currRead.data.range(63, 48); // 2 byte data Order ID
					currentMessageOffset=56;
					setNextState(localMessageType);
				}

			}


			break;

 

Warning message about violation:

[HLS 200-871] Estimated clock period (8.0239ns) exceeds the target (target clock period: 10ns, clock uncertainty: 2.7ns, effective delay budget: 7.3ns)
[HLS 200-1016] The critical path in module 'process_message' consists of the following:	fifo read on port 'stream2parser' (C:/Xilinx/Vitis_HLS/2020.2/common/technology/autopilot/hls_stream_39.h:145) [27]  (3.55 ns)
	'store' operation ('currentMessageLength_V_write_ln187', protocol/src/parser.cpp:187) of variable 'shl_ln' on static variable 'currentMessageLength_V' [54]  (1.95 ns)
	blocking operation 2.53 ns on control path)
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1 Solution

Accepted Solutions
wenchen
Moderator
Moderator
652 Views
Registered: ‎05-27-2018

Hi @KKilic 

I had developed a protocol parser using the Vitis HLS. And I don't see any clue in your posted code that lead to the timing violation. I've got two questions for you.

Which version of Vitis HLS are you using? As far as I know, 2020.2 works much better than 2020.1.

What's your clocking targets? 100M? Have you run the vivado place&route in HLS?  The blocking operation 2.53 ns can be shortened after running the vivado place&route.

In Vitis HLS we consider more scenarios when estimating critical path delay. That's why you see the additional delay. This, in general, helps timing correlation with Vivado but there will be outliers since at the HLS stage we don't have all the necessary information for the critical path. The design will be functionally correct if it meets timing after Vivado P&R.

Thanks,

Wen

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3 Replies
wenchen
Moderator
Moderator
653 Views
Registered: ‎05-27-2018

Hi @KKilic 

I had developed a protocol parser using the Vitis HLS. And I don't see any clue in your posted code that lead to the timing violation. I've got two questions for you.

Which version of Vitis HLS are you using? As far as I know, 2020.2 works much better than 2020.1.

What's your clocking targets? 100M? Have you run the vivado place&route in HLS?  The blocking operation 2.53 ns can be shortened after running the vivado place&route.

In Vitis HLS we consider more scenarios when estimating critical path delay. That's why you see the additional delay. This, in general, helps timing correlation with Vivado but there will be outliers since at the HLS stage we don't have all the necessary information for the critical path. The design will be functionally correct if it meets timing after Vivado P&R.

Thanks,

Wen

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.


**~ Got a minute? Answer our Vitis HLS survey here! ~**


-------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

View solution in original post

KKilic
Observer
Observer
602 Views
Registered: ‎01-01-2021

Hi, It is Vitis HLS 2020.2.

I tried 100mhz and 156Mhz. Even 100Mhz gives this warning.

My target board is Zybo Z7-20 (xc7z020clg400-1). 

 

No I hadn`t tried place and route.

Could you please tell me how I can check  timing values after Vivado P&R ?

I think after implementation, I still have problems.

 

Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 1.928ns (required time - arrival time)
Source: bd_0_i/hls_inst/inst/stream2itch_U/mOutPtr_reg[3]/C
(rising edge-triggered cell FDSE clocked by ap_clk {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: bd_0_i/hls_inst/inst/process_itch_message_U0/currentITCHMessageOffset_V_reg[10]/R
(rising edge-triggered cell FDRE clocked by ap_clk {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: ap_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (ap_clk rise@10.000ns - ap_clk rise@0.000ns)
Data Path Delay: 7.464ns (logic 1.941ns (26.004%) route 5.523ns (73.996%))
Logic Levels: 7 (LUT2=2 LUT3=1 LUT4=1 LUT6=2 SRL16E=1)
Clock Path Skew: -0.049ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.924ns = ( 10.924 - 10.000 )
Source Clock Delay (SCD): 0.973ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

 

 

 

 

 

 

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wenchen
Moderator
Moderator
565 Views
Registered: ‎05-27-2018

Hi @KKilic ,

Please click on the export RTL button and select the vivado place and route option. For more info please infer to the vitis HLS user guide.

Wen

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.


**~ Got a minute? Answer our Vitis HLS survey here! ~**


-------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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