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Participant wdavidlee
Participant
8,517 Views
Registered: ‎02-21-2015

Top level function with ap_ctrl_hs interace but some ports are s_axilite. Error during co-sim.

Hi,

Summary: Specifying ap_ctrl_hs as the top-level interface and s_axilite for some of the ports gives the following error during cosimulation:

@I [SIM-333] Generating C post check test bench ...
@I [SIM-12] Generating RTL test bench ...
@E [SIM-372] This design has AXI_lite interface port but function-level handshaking signals are not bundled to AXI_lite slave.
@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***

Note that the synthesized IP has both the AXI slave interface and the ap_ctrl_hs interface as desired, and I am in the process of verifying its functionality. This error seems reasonable. The presence of the AXI slave interface causes cosim to assume that the user also wants funtion level AXI control. The presence of 2 function level interfaces makes it upset. I get that.

 

My question is this: Is there a directive that tells cosim which interface to use?

 

Workaround: I belive I can just comment out the ap_ctrl_hs pragma during testing.

 

Objective: I'll describe my objective in case you can tell me another way to achieve my goal. I have a function that takes about a dozen configuration parameters. These parameters are computed by the PS, so the AXI slave is a convenient way to set them.

 

One port is driven by a high speed ADC, so it uses ap_hs. When the ADC result is available, I'd like to assert the function level signal ap_start thus I need the ap_crtl_hs interface in addition to the AXI slave interface.

 

Here's a summary of the combinations I've tried. Disclaimer: This is for illustration, not my actual function.

 

#include "hls_macc.h"
void hls_macc(int32 a, int b, int *accum, bool accum_clr) {

//Top level function interface is AXI Slave. All ports controlled by AXI Slave.
//This works fine.
/*
#pragma HLS INTERFACE s_axilite port=return bundle=HLS_MACC_PERIPH_BUS
#pragma HLS INTERFACE s_axilite port=a bundle=HLS_MACC_PERIPH_BUS
#pragma HLS INTERFACE s_axilite port=b bundle=HLS_MACC_PERIPH_BUS
#pragma HLS INTERFACE s_axilite port=accum bundle=HLS_MACC_PERIPH_BUS
#pragma HLS INTERFACE s_axilite port=accum_clr bundle=HLS_MACC_PERIPH_BUS
*/

//Top level function interface is AXI Slave. All ports (except accum) controlled by AXI Slave.
//This works fine.
/*
#pragma HLS INTERFACE s_axilite port=return bundle=HLS_MACC_PERIPH_BUS
#pragma HLS INTERFACE s_axilite port=a bundle=HLS_MACC_PERIPH_BUS
#pragma HLS INTERFACE s_axilite port=b bundle=HLS_MACC_PERIPH_BUS
#pragma HLS INTERFACE ap_hs port=accum
#pragma HLS INTERFACE s_axilite port=accum_clr bundle=HLS_MACC_PERIPH_BUS
*/

//Top level function interface is handshake. All ports (except accum) controlled by AXI Slave.
//Gives error:
//	@I [SIM-333] Generating C post check test bench ...
//	@I [SIM-12] Generating RTL test bench ...
//	@E [SIM-372] This design has AXI_lite interface port but function-level handshaking signals are not bundled to AXI_lite slave.
//	@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***
//

#pragma HLS INTERFACE ap_ctrl_hs port=return
#pragma HLS INTERFACE s_axilite port=a bundle=HLS_MACC_PERIPH_BUS
#pragma HLS INTERFACE s_axilite port=b bundle=HLS_MACC_PERIPH_BUS
#pragma HLS INTERFACE ap_hs port=accum
#pragma HLS INTERFACE s_axilite port=accum_clr bundle=HLS_MACC_PERIPH_BUS


   static acc_reg = 0;
   if (accum_clr) {
      acc_reg = 0;
   }
   acc_reg += a * b;
   *accum = acc_reg;
}

 

Cheers,

David

 

2 Replies
Visitor pi@ugent
Visitor
5,473 Views
Registered: ‎04-19-2016

Re: Top level function with ap_ctrl_hs interace but some ports are s_axilite. Error during co-sim.

Hi,

 

I've got the same problem. Did you ever find a solution? (except for your workaround)

 

Pi

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Highlighted
Explorer
Explorer
1,253 Views
Registered: ‎08-26-2014

Re: Top level function with ap_ctrl_hs interace but some ports are s_axilite. Error during co-sim.

Hello,

 

I am having the same problem. If I use the AXI-Lite to control the IP and to set the parameters, Vivado HLS compiles, the co-simulation passes, and the IP works fine on the Zynq.

 

However, if I use AXI-Lite to set some parameters, and I set the control of the IP as ap_ctrl_hs, the compiler throws the same error as @wdavidlee:

 

ERROR: [COSIM 212-372] This design has AXI_lite interface port but function-level handshaking signals are not bundled to AXI_lite slave.
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***

Does anyone know how to implement an IP using AXI-Lite for some parameters, but the control of the IP using ap_start, ap_done, etc.?

 

Many thanks,

 

Cerilet

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