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Observer
Observer
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Registered: ‎11-07-2017

UG871 RTL Verifications labs failure

I can't get the UG871 "RTL Verifications" labs1 to 3 to compile the test bench correctly. In lab1 to 3 and with Vivado HLS 2017.3 and 2017.2 "vivado_hls -f run_hls.tcl" fails with the following message.

...

INFO: [HLS 200-10] Adding design file 'duc.c' to the project
INFO: [HLS 200-10] Adding design file 'srrc.c' to the project
INFO: [HLS 200-10] Adding design file 'imf1.c' to the project
INFO: [HLS 200-10] Adding design file 'imf2.c' to the project
INFO: [HLS 200-10] Adding design file 'imf3.c' to the project
INFO: [HLS 200-10] Adding design file 'mixer.c' to the project
INFO: [HLS 200-10] Adding design file 'dds.c' to the project
INFO: [HLS 200-10] Adding design file 'mac.c' to the project
INFO: [HLS 200-10] Adding test bench file 'duc_test.c' to the project
INFO: [HLS 200-10] Adding test bench file 'golden' to the project
INFO: [HLS 200-10] Opening and resetting solution '/home/axel/src/electronics/fpgas/xilinx/Vivado_HLS_Tutorial/RTL_Verification/lab3/duc_prj/solution1'.
INFO: [HLS 200-10] Cleaning up the solution database.
INFO: [HLS 200-10] Setting target device to 'xc7k160tfbg484-1'
INFO: [SYN 201-201] Setting up clock 'default' with a period of 2.71ns.
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
ERROR: [SIM 211-100] CSim failed with errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
4
while executing
"source [lindex $::argv 1] "
("uplevel" body line 1)
invoked from within
"uplevel \#0 { source [lindex $::argv 1] } "

INFO: [Common 17-206] Exiting vivado_hls at Tue Nov 7 15:34:13 2017...

 

It appears not be a compilation error. (How would one find out for sure ?)

I tried to compile the test_bench by hand with the project settings I found("all options"), but could only succeed if I didn't use "apint_get_bit" in "imf3.c".  "__bitwidthof__" was nowhere defined on the system.

After I successfully compiled the test_bench it only ran in the debugger but would core-dump when run on the console.

 

Any ideas.

 

Thanks. 

 

BTW: I am using Ubuntu 16.04.2

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