Unable to export xf::security::rsa using Vivado HLS 2019.1

[ansonsit]

Hello,

I am testing the xf::security::rsa function in the Vitis Library using Vivado HLS 2019.1.

When I tried to export it in RTL as an IP, it is stuck with the following messages for days without any further warning.

INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs

Please find attached the log file for your reference. Thank you.

[shameera]

HI @ansonsit ,

Have you tried using HLS 2019.2 ? Can you please confirm if you are using the files present at this link  ?

[ansonsit]

I have updated Vivado to 2019.2, but it was stuck in the same place.

Yes, I used the files in the repo.

[shameera]

HI @ansonsit ,

I have sent you an archive through the EZMove package. That archive consists of HLS files and the logs which show that the design was exported without any issues.

To run the design, from Vivado HLS TCL Shell please use the command vivado_hls -f run_hls.tcl

[ansonsit]

Thank you @shameera.

I have tried your files. I found that the design could be successfully exported for device xcku3p-ffva676-2-e, but it was stuck again when I changed it to xcvu9p-fsgd2104-2L-e. It also didn't work even I increase the clock period to 10ns.

Is it the device issue?

[shameera · Accepted solution]

Hi @ansonsit,

Rather than synthesizing & Implementing while exporting the IP, directly export the IP by modifying the script using the below command

export_design -rtl verilog -format ip_catalog