cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
318 Views
Registered: ‎12-06-2018

Unable to fully partition array assigned to RAM_S2P_LUTRAM

Jump to solution

I am trying to completely partition an array so that I have full access to all of its elements in parallel. I need to perform a read and a write in one cycle, every cycle, which I indicate by placing a PIPELINE II=1 pragma at the beginning of the loops that need to be executed in parallel in the 'main_sys_array' module.

My approach for handling the array partitioning was as follows:

float arr[X][Y];
#pragma HLS RESOURCE variable=arr core=RAM_S2P_LUTRAM
#pragma HLS ARRAY_PARTITION variable=arr complete dim=0

I have reattempted everything with with arr being declared as a 1-dimensional array of size X*Y, but it produced the exact same errors.

During hw_emu I get the following warnings:

WARNING: [XFORM 203-105] Ignore complete array partition directive on 'arr' (/kernel/src/matmul_comp.cpp:316) in dimension 1: conflict with memory core assignment directive.
...
WARNING: [SCHED 204-69] Unable to schedule 'load' operation ('arr_load_2', /home/kernel/src/matmul_comp.cpp:243) on array 'arr' due to limited memory ports. Please consider using a memory core with more ports or partitioning the array 'arr'.

If I remove the RESOURCE pragma, both warnings go away, but the I get the following warning:

WARNING: [SCHED 204-68] The II Violation in module 'main_sys_array' (Function: main_sys_array): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1)
   between wire write on port 'arr_3' (/home/dav114/kernel/src/matmul_comp.cpp:251) and wire read on port 'arr_3' (/kernel/src/matmul_comp.cpp:243).

I am compiling this for an Alveo U250 and currently X=4 and Y=4.

I have no requirement on which specific resource this data is loaded, as long as it allows for the PIPELINE II=1 pragma to be fulfilled.

Thank you in advance!

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
283 Views
Registered: ‎09-04-2017

@dav114   you are using float types. If your next iteration is dependent on the value which is not yet available you might see this issue. 

Expression balancing will not happen by default for float types. Try this option

config_compile -unsafe_math_optimizations

Dont use the resource pragma

Thanks,

Nithin

View solution in original post

1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
284 Views
Registered: ‎09-04-2017

@dav114   you are using float types. If your next iteration is dependent on the value which is not yet available you might see this issue. 

Expression balancing will not happen by default for float types. Try this option

config_compile -unsafe_math_optimizations

Dont use the resource pragma

Thanks,

Nithin

View solution in original post