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Observer jzw
Observer
6,520 Views
Registered: ‎10-31-2013

Using AXIS FIFO with HLS 2013 and Zynq

Hello

 

I have a Zynq system with a AXI_DMA IP and an IP written using HLS. In the HLS code I have the pragmas

 

void Filter(float * piOutData, int * piInData, char * pchLast, char * chDiag)
{
#pragma HLS RESOURCE variable=piOutData core=AXI4Stream
#pragma HLS INTERFACE ap_fifo port=piOutData depth=10*2048
#pragma HLS INTERFACE ap_hs port=piInData

 

Looking at the activity using a logic analyser on the chDiag port I would expect to see the FIFO absorbing data while the DMA process on the Zynq PS is not active, allowing continuous transfer of date through my HLS filter. I am only seeing some 24 4byte words going into the FIFO before stoping.

 

I would appeciate any comments.

 

Thanks Jon

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4 Replies
Xilinx Employee
Xilinx Employee
6,514 Views
Registered: ‎08-17-2011

Re: Using AXIS FIFO with HLS 2013 and Zynq

Hhello Jon,

 

just a random comment that you'll need to double check.. this line may not be correct

#pragma HLS INTERFACE ap_fifo port=piOutData depth=10*2048

 

I recall you can't have expressions in pragmas, so something like this would be needed:

const int my_calculated_depth=10*2048;

#pragma HLS INTERFACE ap_fifo port=piOutData depth=my_calculated_depth

 

and last but not least - #defines with expressions in #pragmas definitely won't work!

 

 

 

Do all the csims/cosims work prior to testing in the FPGA?

 

- Hervé

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Observer jzw
Observer
6,504 Views
Registered: ‎10-31-2013

Re: Using AXIS FIFO with HLS 2013 and Zynq

I have tried using a constant as suggested with no effect. I also removed the depth entry and tried again and the results were the same, implying that there is no FIFO in the IP. Is the FIFO implenented inside the HLS IP or is there something else that influences it?

 

On a slight aside can I get at the control signals for the AXI stream interface inside high level code? If I could I could check for available space on the output and implement a FIFO in the high level code, and also check for available input without stalling on the read.

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Moderator
Moderator
6,483 Views
Registered: ‎04-17-2011

Re: Using AXIS FIFO with HLS 2013 and Zynq

You can very well force HLS to implement your storage function in a FIFO.
#pragma HLS RESOURCE variable=<storage_element> core=FIFO

Also, refer to the HLS Synth report to see how your HLS generated code looks like and what all resources were inferred.
Regards,
Debraj
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Xilinx Employee
Xilinx Employee
6,471 Views
Registered: ‎11-28-2007

Re: Using AXIS FIFO with HLS 2013 and Zynq

The FIFO is assumed to be external to the HLS IP.


@jzw wrote:

I have tried using a constant as suggested with no effect. I also removed the depth entry and tried again and the results were the same, implying that there is no FIFO in the IP. Is the FIFO implenented inside the HLS IP or is there something else that influences it?

 

On a slight aside can I get at the control signals for the AXI stream interface inside high level code? If I could I could check for available space on the output and implement a FIFO in the high level code, and also check for available input without stalling on the read.




Cheers,
Jim
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