06-13-2019 03:44 AM
I am trying to design a simple FIR filter with reloadable coefficients using Vivado HLS. As a starting point, I designed a static coefficient FIR filter based on the HLS example design from https://github.com/Xilinx/HLx_Examples/tree/master/DSP/fir_example . The main differences I introduced were streaming interfaces (hls::stream<>) on the FIR filter input and output. I did so, because I am interested in interfacing the FIR filter with other modules through the AXI-Stream interface. The design ("FIR_StaticCoeff.zip") passes C Simulation, C Synthesis and C/RTL Co-Simulation.
Then, I created a second FIR filter version with reloadable coefficients ("FIR_ReloadCoeff.zip"). This second version has 2 modes of operation: in mode 0, it performs FIR filtering on the input data: in mode 1, it reloads the coefficient values with the input data. The coefficients are stored in a static variable implemented as a RAM_1P core. I've also tried to use the RAM_T2P core, but it didn't change anything. The two modes are mutually exclusive, i.e. their corresponding loops are not active at the same time, and in both of them, the input data is received in a streaming fashion. The design passes C Simulation and C Synthesis, but C/RTL Co-Simulation hangs. No error, warning or simulation deadlock is reported.
The two attached .zip files include the files needed to reproduce my observations (with Vivado HLS 2018.2). In each folder, there is a "run_script.tcl" script that will create the project, add sources to it and run C Simulation, C Synthesis and C/RTL Co-Simulation.
So far, all FIR HLS example designs I've found consider static coefficients only. Through my searches in the Xilinx Foruns, I was not able to find a thread on similar challenges to design a FIR filter with non-static coefficients.
Are there any guidelines on how to design such type of filters? How to correctly manage the reading/writing on a static variable across different HLS function calls?
Thank you for your time and attention!
11-29-2019 04:16 AM
good question, I don't understand why there is no awnser...
I would expect there is a way to convert the two extra stream inputs to an axi data interface...
01-02-2020 02:50 PM
Don't know if you ever figured this out but here are my thoughts in hopes that it is helpful and in hopes that someone from Xilinx looks at this and comments. In looking at the code in 2019.2 hls_fir.h it looks like you might be able to call with
fir1.run(in_data_t in[CONFIG_T::input_length * CONFIG_T::num_channels], out_data_t out[CONFIG_T::output_length * CONFIG_T::num_channels], config_t config[CONFIG_T::num_channels], coeff_t reload[CONFIG_T::num_coeffs + ((CONFIG_T::coeff_sets == 1) ? 0 : 1)])
assuming you have set static config.reloadable=true.
This said, my concern and question for Xilinx folks would be will this work? While there arent checks on the value of reload in the header, this parameter is not mentioned at all in Table 30 or 31 of ug902 and there is a comment that makes me think the omission may be intentional.