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Visitor
Visitor
9,260 Views
Registered: ‎10-23-2013

Vector input to Vivado Block

Hi,

 

I'm working on a block of spectrum sensing using Vivado HLS.
This block will be integrated with a VHDL implementation of a Dual-port RAM (a clock is used to write and a faster clock is used to read) that is filled with values from an AD convertor.
To fill the RAM, the AD clock is used (112MHz). This RAM is the input of the sensing block (implemented in C)
But, the sensing block should execute in a faster clock (120MHz).
I'm having problems to copy the values from the Dual-port RAM to the sensing block, because I don't know how the signal generated by the Vivado HLS work.
I tried to declare a vector as input to the sensing block, that was synthetized as a memory. After pulse the ap_start, I copy each position from the RAM to the sensing block, passing the data and an address to the sensing block.
However, when the ap_done is high, the output of the spectrum sensing is always zero.
I performed a lot of tests in the C code with CMokery library to validate the implementation, and it works fine in the C simulation.

 

Anyone can help?

 

Thanks,

 

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8 Replies
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Xilinx Employee
Xilinx Employee
9,233 Views
Registered: ‎03-24-2010

How about C/RTL Co-simulation?

When you saying "copy the values from the Dual-port RAM to the sensing block", do you integerate the HLS output with your rtl design?

Regards,
brucey
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Visitor
Visitor
9,228 Views
Registered: ‎10-23-2013

Yes, I'm trying to pass the values stored in the dual-port RAM (VHLD design) to the sensing block created on Vivado HLS and synthesized with ISE (a .ngc file). This integration is synthesized using ISE. The resulting .bin is recorded in a Virtex 6 board, developed specifically for this project.

 

At each clock cycle (the faster one) when the ap_ready is up, a value form the RAM is read and copied  to the sensing block.

I implemented the sensing with two inputs: the value received from the RAM and an address to store the value in a internal memory of the sensing block (an static vector in C). The sensing block output is an integer (with 32 bits)

When the sensing done is up, it is ready to read the next value from the RAM.

After 256 reads (size of the RAM), the output of  the sensing block will be valid (before it the internal RAM was incomplete).

However, the sensing output value is always zero.

 

P.S.: When the sensing block is evaluated with a C test bench (using Vivado HLS), the sensing appears to be correct.

 

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Teacher
Teacher
9,225 Views
Registered: ‎03-31-2012

I have seen several people complain about HLS and block ram connectivity. It seems there is an issue with the generated RTL in terms of address signals to the block ram. Can you try 2013.3 ?
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Visitor
Visitor
9,219 Views
Registered: ‎10-23-2013

We have an academical license of Vivado HLS version 2012.4.
I don't know if is possible to use a newest version.
I will try generate a new license and post the results.

Thanks!
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Xilinx Employee
Xilinx Employee
9,202 Views
Registered: ‎11-28-2007

Can add a chipscope ILA core to your design and capture waveform of signals on the HLS block?

 

 

 


@lbondan wrote:

Yes, I'm trying to pass the values stored in the dual-port RAM (VHLD design) to the sensing block created on Vivado HLS and synthesized with ISE (a .ngc file). This integration is synthesized using ISE. The resulting .bin is recorded in a Virtex 6 board, developed specifically for this project.

 

At each clock cycle (the faster one) when the ap_ready is up, a value form the RAM is read and copied  to the sensing block.

I implemented the sensing with two inputs: the value received from the RAM and an address to store the value in a internal memory of the sensing block (an static vector in C). The sensing block output is an integer (with 32 bits)

When the sensing done is up, it is ready to read the next value from the RAM.

After 256 reads (size of the RAM), the output of  the sensing block will be valid (before it the internal RAM was incomplete).

However, the sensing output value is always zero.

 

P.S.: When the sensing block is evaluated with a C test bench (using Vivado HLS), the sensing appears to be correct.

 




Cheers,
Jim
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Visitor
Visitor
9,193 Views
Registered: ‎10-23-2013

How can I do it?

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Moderator
Moderator
9,166 Views
Registered: ‎04-17-2011

Add Chipscope Definition File (CDC) in your ISE project and then open it to map the signals from the HLS block to debug. Look for Chipscope tutorial in xilinx.com website.
Regards,
Debraj
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Visitor
Visitor
9,160 Views
Registered: ‎10-23-2013

Thanks Debraj.

 

I will try it and post the results.

 

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