UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer anujvaishnav
Observer
440 Views
Registered: ‎11-06-2017

Vectorize AXI interface with Vivado HLS when resynthesizing

Hi,

I have noticed that during development with Vivado HLS if we vectorize the scalar input and output parameters AXI interface's data width does not change correspondingly when resynthesized. One has to recreate the entire project for the change to be reflected in AXI interface.

Does anyone know a way to avoid the recreation of projects or generate a warning when synthesizing?

I attempted this on Vivado 16.4, Vivado 17.3 and Vivado 18.2 with Ubuntu 16.04 LTS.

Regards,

Anuj

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
368 Views
Registered: ‎09-05-2018

Re: Vectorize AXI interface with Vivado HLS when resynthesizing

Hey @anujvaishnav ,

I'm not sure I totally understand the issue. Maybe it would be clearer if you provided some code.

It might be easier to remove just the 'syn' folder rather than the entire project.

Nicholas Moellers

Xilinx Worldwide Technical Support
0 Kudos
Observer anujvaishnav
Observer
347 Views
Registered: ‎11-06-2017

Re: Vectorize AXI interface with Vivado HLS when resynthesizing

Hi @nmoeller,

If you write following snippet and synthesize Vivado HLS generates AXI data width of 32 bit wide.

a) 

__kernel void __attribute__ ((reqd_work_group_size(WG_X, 1, 1)))
vadd(global int* a,
global int* b,
global int* c)
{

int idx = get_global_id(0);
c[idx] = a[idx] + b[idx];

}

But if you then change it int4 and synthesize it remains 32 bit wide.

b)

__kernel void __attribute__ ((reqd_work_group_size(WG_X, 1, 1)))
vadd(global int4* a,
global int4* b,
global int4* c)
{

int idx = get_global_id(0);
c[idx] = a[idx] + b[idx];

}

Now if you create a new project with source code b) and synthesize, it suddenly generates 128 bit data width as you would expect.

I think Vivado HLS keeps some sort of local state inside which dictates its AXI width. However, it seems to me more of a bug.

0 Kudos