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Paolo_Palazzari
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Registered: ‎06-25-2021

Vitis Co-simulation: the C simulation is working while the co-simulation sees an error in the testbench

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Hi all,
I am quite new to the Vitis environment and I am trying to implement some basic algorithm to try to have control over what is happening with the HLS. For this reason, I was trying to run the co-simulation of an algorithm computing the scalar product between two vectors. I prepared the testbench to properly initialize the vectors and I performed the C simulation, obtaining the expected result

INFO: [SIM 2] *************** CSIM start ***************
INFO: [SIM 4] CSIM will launch GCC as the compiler.
make: 'csim.exe' is up to date.
INFO: [SIM 1] CSim done with 0 errors.
INFO: [SIM 3] *************** CSIM finish ***************

After this, I tried to run the co-simulation, but this time I got the error message informing me that the C testbench was returning wrong results

INFO: [COSIM 212-302] Starting C TB testing ...
ERROR: [COSIM 212-359] Aborting co-simulation: C TB simulation failed, nonzero return value '1'.
ERROR: [COSIM 212-320] C TB testing failed, stop generating test vectors. Please check C TB or re-run cosim.
ERROR: [COSIM 212-5] *** C/RTL co-simulation file generation failed. ***
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***


I checked the C testbench, but I did not find the root of the problem.

I attach the Vitis project (including the testbench). Do you see any error/reason that could explain why I am not able to co-simulate?

Thanks for any help/advice.

Paolo

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randyh
Xilinx Employee
Xilinx Employee
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Registered: ‎01-04-2013

Hi Paolo, I actually just created a Vitis HLS project from your source files. That is why my project was targeting a different device. I looked at your Vitis HLS project, and one difference is that my krnl_scalar_product.cpp uses the following pragmas, which seem to work in your project as well:

#pragma HLS INTERFACE m_axi port=in1 bundle=in1_port depth=512
#pragma HLS INTERFACE m_axi port=in2 bundle=in2_port depth=512
#pragma HLS INTERFACE m_axi port=out_r bundle=in1_port

 

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randyh
Xilinx Employee
Xilinx Employee
488 Views
Registered: ‎01-04-2013

In the Guidance window in the Vitis HLS GUI you will see a note or warning like "Cosim warning that says "AXI_master port "in1" has a depth of 0. Insufficient depth may result in simulation mismatch or freeze."

If you add the depth property to your m_axi Interface pragmas, it may help (note, in my test I set DATA_SIZE to 32):
#pragma HLS INTERFACE m_axi port=in1 bundle=in1_port depth=32

This is discussed in another forum post:
https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Co-simulation-errors-with-AXI-master-and-depth/td-p/775822

And also in the docs (apparently), look at the depth option:
https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/hls_pragmas.html#jit1504034365862

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Paolo_Palazzari
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Registered: ‎06-25-2021

Thanks for pointing me to the docs. I added the depth option, trying both the form

void krnl_scalar_product(volatile const float *in1, // Read-Only Vector 1
volatile const float *in2, // Read-Only Vector 2
volatile float *out_r, // Output Result
const int size // Size in integer
) {

#pragma HLS INTERFACE m_axi port=in1 depth=512 bundle=in1_port
#pragma HLS INTERFACE m_axi port=in2 bundle=in2_port
#pragma HLS INTERFACE m_axi port=out_r depth=512 bundle=in1_port

 

and the other form, moving the depth option at the end of the pragma as in the following

void krnl_scalar_product(volatile const float *in1, // Read-Only Vector 1
volatile const float *in2, // Read-Only Vector 2
volatile float *out_r, // Output Result
const int size // Size in integer
) {

#pragma HLS INTERFACE m_axi port=in1 bundle=in1_port depth=512 
#pragma HLS INTERFACE m_axi port=in2 bundle=in2_port
#pragma HLS INTERFACE m_axi port=out_r bundle=in1_port depth=512

In both the case I still see the message

 

INFO: [COSIM 212-14] Instrumenting C test bench ...
WARNING: [COSIM 212-369] AXI_master port 'in1' has a depth of '0'. Insufficient depth may result in simulation mismatch or freeze.
WARNING: [COSIM 212-369] AXI_master port 'out_r' has a depth of '0'. Insufficient depth may result in simulation mismatch or freeze.
Build using "/opt/xilinx/vitis/2020.2/Vitis_HLS/2020.2/tps/lnx64/gcc-6.2.0/bin/g++"
Compiling krnl_testbench.cpp_pre.cpp.tb.cpp
Compiling apatb_krnl_scalar_product.cpp
Compiling krnl_scalar_product.cpp_pre.cpp.tb.cpp
Compiling apatb_krnl_scalar_product_ir.ll
Generating cosim.tv.exe
INFO: [COSIM 212-302] Starting C TB testing ...
ERROR: [COSIM 212-359] Aborting co-simulation: C TB simulation failed, nonzero return value '1'.
ERROR: [COSIM 212-320] C TB testing failed, stop generating test vectors. Please check C TB or re-run cosim.

Does someone see what is wrong with my design?

 

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randyh
Xilinx Employee
Xilinx Employee
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Registered: ‎01-04-2013

I did add some print statements to your testbench so I could see what was going on in the code, but otherwise it is unchanged.  

image.png
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Paolo_Palazzari
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Registered: ‎06-25-2021

Hi @randyh ,

  thanks for your support. I see that we are using the same version of vitis_hls but, looking at your screenshot, I see that you are addressing a different target. As you added only few prints, I wonder if there are some different defaults for the project (i.e. configuration values not exported in the vitis_hls project but taken from the environment). I say this because I tried doing what I suppose you did (downloading the archive project I attached to this discussion, importing it in vitis, adding the depth=512 parameter to the INTERFACE pragma, compiling for HW emulation, opening the vitis_hls project and performing the co-simulation) and, again, my co-simulation failed (see attached screenshot). For this reason I archived the vitis_hls project (the one which is failing) and I attach it to this discussion. Should you see any reason explaining why I am failing, please let me know. In case, could you please send me the archive of your working vitis_hls project so that I can meld it with my project and search for different configuration values? Thanks again for your kind help.

 

 

screenshot_1.jpg
screenshot_2.jpg
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randyh
Xilinx Employee
Xilinx Employee
321 Views
Registered: ‎01-04-2013

Hi Paolo, I actually just created a Vitis HLS project from your source files. That is why my project was targeting a different device. I looked at your Vitis HLS project, and one difference is that my krnl_scalar_product.cpp uses the following pragmas, which seem to work in your project as well:

#pragma HLS INTERFACE m_axi port=in1 bundle=in1_port depth=512
#pragma HLS INTERFACE m_axi port=in2 bundle=in2_port depth=512
#pragma HLS INTERFACE m_axi port=out_r bundle=in1_port

 

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