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dsakjl
Voyager
Voyager
286 Views
Registered: ‎07-20-2018

Vitis HLS 2020.2: AXI4-Lite separated clock

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Hello everyone,

from Vitis HLS 2020.2 documentation (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1399-vitis-hls.pdf), section "Managing Interfaces/AXI4-Lite Interface/Control Clock and Reset in AXI4-Lite Interfaces" it seems possible to add a separated clock for axi-lite interfaces (one clock per bundle).

I tried to use this option on an interface pragma as following:

#pragma HLS INTERFACE s_axilite port=add0 bundle=ctrl clock=axil_aclk

but after synthesis, no clock port is generated other than the usual ap_clk.

Please, can you help me on this?

Thank you, best regards.

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randyh
Xilinx Employee
Xilinx Employee
168 Views
Registered: ‎01-04-2013

There are plans to restore it at the next opportunity. 

View solution in original post

4 Replies
randyh
Xilinx Employee
Xilinx Employee
249 Views
Registered: ‎01-04-2013

This is a bug in the tool. It is available in Vivado HLS, but not Vitis HLS. Sorry.

dsakjl
Voyager
Voyager
209 Views
Registered: ‎07-20-2018

Hi @randyh ,

thank you for the reply. Do you know if this option will be available in the next release of Vitis HLS or will be just removed from the documentation?

Thank you, best regards.

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df0101
Contributor
Contributor
182 Views
Registered: ‎06-25-2018

I have also run into this recently.  It would be a useful feature to restore to vitis_hls.

randyh
Xilinx Employee
Xilinx Employee
169 Views
Registered: ‎01-04-2013

There are plans to restore it at the next opportunity. 

View solution in original post