03-16-2021 08:16 AM
from Vitis HLS 2020.2 documentation (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1399-vitis-hls.pdf), section "Managing Interfaces/AXI4-Lite Interface/Control Clock and Reset in AXI4-Lite Interfaces" it seems possible to add a separated clock for axi-lite interfaces (one clock per bundle).
I tried to use this option on an interface pragma as following:
#pragma HLS INTERFACE s_axilite port=add0 bundle=ctrl clock=axil_aclk
but after synthesis, no clock port is generated other than the usual ap_clk.
Please, can you help me on this?
Thank you, best regards.
03-17-2021 01:47 AM