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suguri
Observer
Observer
390 Views
Registered: ‎01-08-2020

Vitis HLS 2021.1 axis synthesis problem

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Hi,

 

I have test code.

 

typedef ap_axiu<8,0,0,0> dataWord;

void test(hls::stream<dataWord>& in){
    #pragma HLS INTERFACE axis name=in port=in
    dataWord a;
    a = in.read(); // or in.read(a);
}

 

I get an error as a result of synthesis.

ERROR: [XFORM 203-801] Interface read on 'in_1' has incompatible types. Possible cause(s): data pack is only applied on source(port) or destination(variable).

ERROR: [HLS 200-70] Failed building synthesis data model.

 

This test code was fine on 2020.1 2020.2.

 

Thank you.

 

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1 Solution

Accepted Solutions
randyh
Xilinx Employee
Xilinx Employee
299 Views
Registered: ‎01-04-2013

It appears to be related to your pragma. The following works in 2021.1:

#pragma HLS INTERFACE axis port=in

I will report the issue. 

View solution in original post

2 Replies
suguri
Observer
Observer
343 Views
Registered: ‎01-08-2020

Additional, C, C++ native types work fine. ( int, unsigned int, unsigned char...)

In the end, the ap_axiu and ap_axis types seem to be the problem.

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randyh
Xilinx Employee
Xilinx Employee
300 Views
Registered: ‎01-04-2013

It appears to be related to your pragma. The following works in 2021.1:

#pragma HLS INTERFACE axis port=in

I will report the issue. 

View solution in original post