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pswetalina
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Registered: ‎12-04-2014

Vivado HLS BRAM and ap_memory usage.

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Hi.

 

I have an IP created in Vivado HLS for a simple module which takes in arrays as input arguments. Now I use the "ap_memory" interface and "1-Port BRAM" resource directive for the arrays. I used this IP to integrate with the Zynq processing System in Vivado and make all the connections. The thing is I do not have a BRAM in my block design. But still all my values are getting written and processed.

 

Where is it stored then if I do not have a memory generator block in my design?

 

Thanks.

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debrajr
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Registered: ‎04-17-2011
Have you checked the generated RTL(VHDL/Verilog) files in HLS after Csynth. That would give you a clue!
Regards,
Debraj
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debrajr
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Registered: ‎04-17-2011
Have you checked the generated RTL(VHDL/Verilog) files in HLS after Csynth. That would give you a clue!
Regards,
Debraj
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pswetalina
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Registered: ‎12-04-2014

Thanks for the reply.

 

I want to connect my IP to an external BRAM. I have 5 arrays as input arguments. Is it possible to bundle all the input ports to a single input port and connect it to an external BRAM in Vivado. 

 

There are tutorials lacking on BRAM usage for both Vivado 2014.2 and Vivado HLS. 

 

Thanks again!

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debrajr
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Registered: ‎04-17-2011
Even if you bundle, how are you planning to drive them in your design?
Regards,
Debraj
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