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Registered: ‎12-26-2018

[Vivado HLS Co-simulation] Waveform signals never change

I have been trying to run the C/RTL co-simulation of my design which is written in C using Vivado HLS. Below is an example of the waveform during the co-simulation. From the figure, all signal values do not seem to change at all (except clk and a few others), and for this reason (I believe) the co-simulation never finish even I run for a day.


The top module is defined as below. Here, I would like to see the value of variables such as load_count, compute_count, store_count in the co-simulation waveform. How would I find signals of these variables? I can't find any of these values in either of the 3 groups of waveform signal:

  • AESL_inst_top
  • Design Top Signal
  • Test bench Signals


void top(
uint32_t inst_count,
volatile vec_T * inst_buffer,
volatile vec_T *...) {

// pragmas --------------------------------------------------------
#pragma HLS INTERFACE s_axilite port=insn_count bundle=CONTROL_BUS
#pragma HLS INTERFACE m_axi depth=7 port=inst_buffer offset=slave bundle=ins_port

// Variables ------------------------------------------------------ hls::stream<vec_T> load_queue; hls::stream<vec_T> compute_queue; hls::stream<vec_T> store_queue; #pragma HLS stream variable=load_queue depth=10 dim=1 #pragma HLS stream variable=compute_queue depth=10 dim=1 #pragma HLS stream variable=store_queue depth=10 dim=1 ... // Load instructions inst_buffer from into load/compute/store queue ... // Main loop ------------------------------------------------------ while (true) { while (load_module is not waiting for other module) { load_module(load_queue, ...);
load_count++; ... } while (compute_module is not waiting for other module) { compute_module(compute_queue, ...);
compute_count++; ... } while (store_module is not waiting on other module) { store_module(store_queue, ...);
store_count++; ... } ... // Break after executing all instructions } }



Screenshot from 2019-06-14 22-07-50.png


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2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎06-16-2017


I believe you are looking for these signals from the default ones that are already in the view/waveform panel. If so, use the search bar in the name section (2nd column in your photo) for the signals you're looking for and add them to the view waveform panel by dragging them.


As a side note, I see that you're using while loops. It is recommended to convert while loops to for loops if you want to achieve coarse grain pipelining across the loops. To do so you need to -

1. Convert while to for

2. Encapsulate each loop in a sub-function

3. Use #pragma HLS dataflow on top of subfunction


For more details on this refer to dataflow optimization in the latest SDAccel optimization user guide :


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Registered: ‎12-26-2018

@siddhart The while loop is unavoidable. I cannot convert the while loop to for loop because the above C code describe the execution of an instruction stream, which can be executed in an out-of-oder fashion, exactly as in the above code.

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