cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
sggking
Observer
Observer
3,575 Views
Registered: ‎06-12-2017

Vivado HLS Error during C/RTL Cosimulation

Hi,I use HLS fft ip to implement 1K fft.In HLS,there is a example project about fft.The example can work well,but if I copy the source files and create a new project,besides the same input datas are used,the new project can pass the C simulation and the synthesis,while the C/RTL Cosimulation failed.I do not know why this happen.And the errors show like this:

    starting static elaboration

    waring:[VRFC 10-1303] range is empty (null range).....(a lot of such warnings)
    error:[VRFC 10-982] library name xfft_v9_0_9 of instantiated unit conflicts with visble identifier...
    error:[VRFC 10-426] cannot find port xn_address0 on this module[E:/.../solution1/sim/verilog/fft_top.v:267]
    error:[VRFC 10-426] cannot find port xn_ce0 on this module[E:/.../solution1/sim/verilog/fft_top.v:268]
    error:[VRFC 10-426] cannot find port xn_we0 on this module[E:/.../solution1/sim/verilog/fft_top.v:269]
    error:[VRFC 10-426] cannot find port xn_d0 on this module[E:/.../solution1/sim/verilog/fft_top.v:270]
    error:[VRFC 10-426] cannot find port xn_q0 on this module[E:/.../solution1/sim/verilog/fft_top.v:271]
    ...(a lot of such errors,all about the input(xn) and output(xk) datas)
    error:[VRFC 10-426] cannot find port xk_d1 on this module[E:/.../solution1/sim/verilog/fft_top.v:285]
    error:[VRFC 43-3322] static elaboration of top level verilog design unit(s) in library work failed.
    error:please check the snapshot name which is created during 'xelab',the current snapshot name "xsim.dir/fft_top/xsimk.exe"does not exist.
    ***C/RTL co-simulation finished:FAIL ***
 
I try this in HLS 2016.4 and HLS 2017.2,both are failed.

Can anyone help me with the problem? Is there anything wrong with the installation of the vivado HLS? Or something else wrong with my project? Any suggestions?

 

 

10 Replies
sggking
Observer
Observer
3,528 Views
Registered: ‎06-12-2017

Can anyone help me,please?

0 Kudos
sggking
Observer
Observer
3,515 Views
Registered: ‎06-12-2017

@florentw Can you help me.

florentw
Moderator
Moderator
3,504 Views
Registered: ‎11-09-2015

Hi @sggking,

 

If you want somebody to respond to an error like that you might want to attach your project (.zip) to the post. It is easier when an issue can be reproduced.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
sggking
Observer
Observer
3,493 Views
Registered: ‎06-12-2017

@florentw

The project is in the attachments.

0 Kudos
ejhe360
Visitor
Visitor
3,315 Views
Registered: ‎05-10-2017

Hi @sggking

 

Did you find any progress on this issue?

 

I just ran into the same problem with the FFT core in HLS. It looks like the FFT is trying to instantiate some kind of BRAM interface on the IO ports (it's looking for xn_address0, xn_address1, xk_address0, xk_address1, and associated ports...). I'm not sure why it would be doing that, because the actual FFT core does not have those interfaces.

 

Thanks!

 

 

 

 

0 Kudos
sggking
Observer
Observer
3,254 Views
Registered: ‎06-12-2017

Hi@ejhe360
No new progress has been made on this issue. How about you? Any progress?
0 Kudos
ejkreinar
Visitor
Visitor
3,245 Views
Registered: ‎05-10-2017

Hi sggking,

 

I had no success generating HDL from an HLS model with the fft function. I'm really not sure what went wrong... I tried all sorts of permutations of compiler directives, including adding/removing dataflow, adding/removing pipeline, and different IO formats on the input and outputs variables. 

 

Like your tests, I confirmed the default FFT example works successfully, but the only other step remaining I'd perhaps try is to make a direct copy of the FFT example and then incrementally add my application specific content until the example breaks. But, I was discouraged from trying this because it seems as though you already found that a direct copy of the FFT example breaks in the same way I saw.

 

My workaround solution is to split the HLS model into two parts 1) pre-fft and 2) post-fft, and I will wrap a Xilinx-generated FFT IP core in between the two HLS models using verilog, without using HLS to generate the FFT. 

 

This is a real bummer... I'm hoping it gets fixed in more recent versions of HLS (I'm still using 2015.4, but it's disappointing you're finding similar problems in 2016.4 and 2017.2)

sggking
Observer
Observer
2,923 Views
Registered: ‎06-12-2017

Hi ejkreinar,

 

I am not clear about your solution "My workaround solution is to split the HLS model into two parts 1) pre-fft and 2) post-fft, and I will wrap a Xilinx-generated FFT IP core in between the two HLS models using verilog, without using HLS to generate the FFT. " What do you mean "wrap a Xilinx-generated FFT IP core in between the two HLS models using verilog"? Could you please explain more? Thanks very much.

 

Through your method, does your project work well? Is it convenient for you to show me your code? 

 

0 Kudos
frestuc
Observer
Observer
2,076 Views
Registered: ‎05-21-2018

The bug is still there on 2018.2...

 

This is what causes it:

 

fft_config1_s grp_fft_config1_s_fu_519(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(grp_fft_config1_s_fu_519_ap_start),
.ap_ce(grp_fft_config1_s_fu_519_ap_ce),
.ap_done(grp_fft_config1_s_fu_519_ap_done),
.ap_idle(grp_fft_config1_s_fu_519_ap_idle),
.ap_ready(grp_fft_config1_s_fu_519_ap_ready),
.xn_address0(grp_fft_config1_s_fu_519_xn_address0),
.xn_ce0(grp_fft_config1_s_fu_519_xn_ce0),
.xn_we0(grp_fft_config1_s_fu_519_xn_we0),
.xn_d0(grp_fft_config1_s_fu_519_xn_d0),
.xn_q0(32'd0),
.xn_address1(grp_fft_config1_s_fu_519_xn_address1),
.xn_ce1(grp_fft_config1_s_fu_519_xn_ce1),
.xn_we1(grp_fft_config1_s_fu_519_xn_we1),
.xn_d1(grp_fft_config1_s_fu_519_xn_d1),
.xn_q1(32'd0),
.xk_address0(grp_fft_config1_s_fu_519_xk_address0),
.xk_ce0(grp_fft_config1_s_fu_519_xk_ce0),
.xk_we0(grp_fft_config1_s_fu_519_xk_we0),
.xk_d0(grp_fft_config1_s_fu_519_xk_d0),
.xk_q0(32'd0),
.xk_address1(grp_fft_config1_s_fu_519_xk_address1),
.xk_ce1(grp_fft_config1_s_fu_519_xk_ce1),
.xk_we1(grp_fft_config1_s_fu_519_xk_we1),
.xk_d1(grp_fft_config1_s_fu_519_xk_d1),
.xk_q1(32'd0),
.status_data_V_din(grp_fft_config1_s_fu_519_status_data_V_din),
.status_data_V_full_n(1'b1),
.status_data_V_write(grp_fft_config1_s_fu_519_status_data_V_write),
.config_ch_data_V_dout(16'd0),
.config_ch_data_V_empty_n(1'b1),
.config_ch_data_V_read(grp_fft_config1_s_fu_519_config_ch_data_V_read)
);


module fft_config1_s
#(parameter
INPUT_WIDTH = 32,
OUTPUT_WIDTH = 32,
CONFIG_WIDTH = 16,
STATUS_WIDTH = 8
)
(
input wire ap_clk,
input wire ap_rst,
input wire ap_start,
input wire ap_ce,
output reg ap_done,
output reg ap_ready,
output wire ap_idle,
input wire [CONFIG_WIDTH-1:0] config_ch_data_V_dout,
input wire config_ch_data_V_empty_n,
output wire config_ch_data_V_read,
input wire [INPUT_WIDTH-1:0] xn_dout,
input wire xn_empty_n,
output wire xn_read,
output wire [OUTPUT_WIDTH-1:0] xk_din,
input wire xk_full_n,
output wire xk_write,
output wire [STATUS_WIDTH-1:0] status_data_V_din,
input wire status_data_V_full_n,
output wire status_data_V_write
);

 

There are mismatches between variable names in fft_config_1_s instantiations and definitions... 

0 Kudos
tree_tree
Observer
Observer
1,319 Views
Registered: ‎11-30-2018

I have the same problem in my project。Do you solve it??

0 Kudos