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Visitor tapollin
Visitor
4,634 Views
Registered: ‎03-20-2013

Vivado HLS: Example Project from Xilinx doesn't work properly in SysGen

Hi there

 

 

If I export the example project from Vivado HLS "array_ROM" to SysGen in order to simulate, this doesn't work properly.

The output value ap_return is always undefined and not available.

 

I've added a picture which represents the simulation.

 

Do I make something wrong ?

 

Thank you in advance

 

 

sysgenverification.png
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