11-21-2018 07:20 AM
Hi to All.
I'm working on a Background subtraction module using Vivado HLS. I need to introduce the input image, the output image, and more parameters.
I have 4 big vectors that are input/output vectors that are inputted into FPGA, modified and outputted to the cpu to follow its processing in the algorithm. The other parameters are only input parameter. This is the header of the function I'm using.
void apply_fpga(AXI_STREAM& src_in, AXI_STREAM& dst_out, float* weight_frame, float* variance_frame, float* mean_frame, unsigned char* modesUsed_frame, int num_gaussian, int num_channels, int nmixtures, float alphaT, float Tb, float TB, float Tg, float varInit, float varMin, float varMax, float prune, float tau, bool detectShadows, unsigned char shadowVal )
The variable weight_frame, variance_frame, mean_frame, modesUsed_frame are the 4 vectors. At the moment I'm passing them as pointers, In eclipse is working, but 'im not able to simulate the code in vivado HLS. My idea is to run the simulation and to change the type of variable from float to fixed and to choose a good option between space waste on the fpga and performance.
I'm using Axi stream for the input and output image, but I don't know what to use for the vectors, Any suggestion is accepted! Many thanks in advance!
11-22-2018 02:36 AM
How large are these large vectors?
Anything up to a few tens of kilobytes can be put in block RAM reasonably easily. Hundreds of kilobytes is manageable but not great. Above that, I'd start looking at an AXI Master to access the data in off-chip RAM.
11-28-2018 02:14 AM
Thanks for reply, The vector are around 800K and a maximum of 2.5M, they have the dimension of the image because I need to input these values for each pixel, make some calculation and give back to the other part of the algorithm that run on the CPU, So I have a 2 transfers for each frame.
Input, calculation and output. I think to make this interchange with the offchip RAM. Do you recommend using axi?
How much Axi bus I Can Handle? In concrete I have Image_In Image_Out and 4 Vectors.
11-28-2018 05:09 AM
AXI seems like a good option here. Bandwidth of AXI can be huge; but realistically 1 - 2 pixels per cycle is about as much as HLS is ever likely to need.
01-22-2019 09:53 AM
Hi to all,
I'm using the Axi Master for the big vectors, and the AXI Stream for the input output image.
During the Vivado HLS simulation is working correctly, and I can synthesize the IP. The post synthesis simulation is giving me the same results and I can create the IP.
How I can Connect in Vivado the IP, to the Zynq system?
I'm thinking to use two HP port, where one port is connected to the Axi streaming and the other to the Axi Master. In the Axi streaming I have to use an AXI dma IP, but I'm not sure what to use for The AXI Master.
The doubt I have is for Linux Driver too. Because I already have experience reading/writing from the AXI streaming and VDMA, using a device driver with uio and mmap to /dev/uio0 but I do not know how to map the AXI Master to see it from petalinux.
Any help is welcome. Many thanks in advance.