I just started learning SystemC, and I am trying to create a basic 8-Tap moving average FIR filter. But I am having a bit of trouble with VHDL RTL export. The code synthesizes fine in Vivado HLS, and returns utilization numbers, max frequency, etc. But when I run RTL export and try to synthesize the VHDL in Vivado, it returns 0s for utilization, and timing analysis does not work. The runtime logs for Vivado synthesize return two different errors, which are listed below. I read somewhere on these forums that this can be caused by Vivado removing logic due to unconnected ports, but I have no idea how to fix that. I have run other smaller SystemC programs in Vivado HLS, and have had no problem exporting and getting utilization numbers in Vivado for them. Could someone please take a look at my code and let me know what I am doing wrong, and what I need to change?
WARNING: [Synth 8-3331] design FIRFilt_FIRFilt_tbkb has unconnected port reset WARNING: [Synth 8-6014] Unused sequential element FIRFilt_tap_V_load_2_reg_452_reg was removed. [..VivadoFIR/FIRFilt/FIRFilt.srcs/sources_1/imports/vhdl/FIRFilt_prc_FIRFilt.vhd:154]