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alexafi
Observer
Observer
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Registered: ‎11-13-2012

Vivado HLS TCL error during "elaborate" step of ISE synthesis

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Hi!

 

I synthesised a pcore in Vivado HLS. In the pcore/mycore/data folder I have and MPD file with:

OPTION ELABORATE_PROC = elaborate

 

and a TCL file containing this function ("elaborate") and a couple of others.

 

When trying to generate the bitstream for my design that includes this pcore, during the elaborate phase, I get an error that no such function exists.

 

IPNAME:mycore_top INSTANCE:mycore_top_0 -
<some path>/planAhead_projects/zed_hello/zed_hello.srcs/

source
s_1/edk/proc_module/proc_module.mhs line 177 - elaborating IP
ERROR:EDK:2951 -
   Unknown Tcl procedure ::hw_mycore_top_v1_00_a::elaborate
   called
ERROR:EDK - mycore_top_0 (mycore_top) -  
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/proc_module.bmm] Error 2
Done!

 

Could anyone please help me with this?

All tools have version 2012.2, the hardware is Zedboard with Xilinx Zynq SoC.

 

Thanks in advance!

Alex

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alexafi
Observer
Observer
8,820 Views
Registered: ‎11-13-2012
Hi, Herve,

thank you for your reply.

You are right, there is nothing manual to be done. I've already got it working.

The issue was with the name of my pcore - "LBM_performStreamCollide_top_0". Changing it to "lbm_acc_top_0" worked just fine. Is it a bug of the tool?

Best,
Alex

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herver
Xilinx Employee
Xilinx Employee
7,411 Views
Registered: ‎08-17-2011

Hi Alex,

 

There's an issue with your question... You're describing the error, not how you got there...

 

I'm guessing that the VHLS block you generated uses some IP core from coregen, that's usually when I see this option.

How do you call the TCL script, usually there aren't any issues?

 

For example, in my experience, it works from ISE with the EDK-XPS system instantiated from there, itself containing the pcore from VHLS. At some stage, the coregen ip get generated, i'm not doing anything manually with that TCL file.

 

What IPs are you using? - check the xco files in the pcore directory under synhdl/verilog: do you have many?

 

Also you should update to 2012.3 since it's the latest, greatest to date.

 

 

- Hervé

SIGNATURE:
* Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
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alexafi
Observer
Observer
8,821 Views
Registered: ‎11-13-2012
Hi, Herve,

thank you for your reply.

You are right, there is nothing manual to be done. I've already got it working.

The issue was with the name of my pcore - "LBM_performStreamCollide_top_0". Changing it to "lbm_acc_top_0" worked just fine. Is it a bug of the tool?

Best,
Alex

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herver
Xilinx Employee
Xilinx Employee
7,397 Views
Registered: ‎08-17-2011

Hi Alex,

 

There's a issue here with the compatibility between the tools XPS and VHLS.

XPS requires the names to be lower case - page 8 of the Platform Specification Format ref manual

  http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/psf_rm.pdf

"File and IP names must be lower-case to ensure consistency"

 

Vivado HLS will keep the case used for the toplevel in the generated files.

 

Your renaming matched the lower case constraint that XPS has, and solved the issue.

 

- Hervé

SIGNATURE:
* Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
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