11-17-2012 06:17 AM
I synthesised a pcore in Vivado HLS. In the pcore/mycore/data folder I have and MPD file with:
OPTION ELABORATE_PROC = elaborate
and a TCL file containing this function ("elaborate") and a couple of others.
When trying to generate the bitstream for my design that includes this pcore, during the elaborate phase, I get an error that no such function exists.
IPNAME:mycore_top INSTANCE:mycore_top_0 -
s_1/edk/proc_module/proc_module.mhs line 177 - elaborating IP
Unknown Tcl procedure ::hw_mycore_top_v1_00_a::elaborate
ERROR:EDK - mycore_top_0 (mycore_top) -
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/proc_module.bmm] Error 2
Could anyone please help me with this?
All tools have version 2012.2, the hardware is Zedboard with Xilinx Zynq SoC.
Thanks in advance!
11-18-2012 04:56 PM
11-18-2012 03:21 PM - edited 11-18-2012 03:24 PM
There's an issue with your question... You're describing the error, not how you got there...
I'm guessing that the VHLS block you generated uses some IP core from coregen, that's usually when I see this option.
How do you call the TCL script, usually there aren't any issues?
For example, in my experience, it works from ISE with the EDK-XPS system instantiated from there, itself containing the pcore from VHLS. At some stage, the coregen ip get generated, i'm not doing anything manually with that TCL file.
What IPs are you using? - check the xco files in the pcore directory under synhdl/verilog: do you have many?
Also you should update to 2012.3 since it's the latest, greatest to date.
11-18-2012 04:56 PM
11-19-2012 03:10 AM
There's a issue here with the compatibility between the tools XPS and VHLS.
XPS requires the names to be lower case - page 8 of the Platform Specification Format ref manual
"File and IP names must be lower-case to ensure consistency"
Vivado HLS will keep the case used for the toplevel in the generated files.
Your renaming matched the lower case constraint that XPS has, and solved the issue.