11-13-2012 01:42 PM
I synthesised a pcore in Vivado HLS. In the pcore/mycore/data folder I have and MPD file with:
OPTION ELABORATE_PROC = elaborate
and a TCL file containing this function ("elaborate") and a couple of others.
When trying to generate the bitstream for my design that includes this pcore, during the elaborate phase, I get an error that no such function exists. Could anyone please help me with this?
All tools have version 2012.2, the hardware is Zedboard with Xilinx Zynq SoC.
Thanks in advance!
11-14-2012 08:11 AM
This is the exact error message:
IPNAME:mycore_top INSTANCE:mycore_top_0 -
s_1/edk/proc_module/proc_module.mhs line 177 - elaborating IP
Unknown Tcl procedure ::hw_mycore_top_v1_00_a::elaborate
ERROR:EDK - mycore_top_0 (mycore_top) -
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/proc_module.bmm] Error 2
11-18-2012 02:57 PM - edited 11-18-2012 03:04 PM
Please do not post the same question on multiple forums, for example see:
Also please appreciate that most people don't work on the weekend so you can't get a response any faster when posting on different forums anyway. At the moment the forum for Vivado HLS questions is one of the 4 forums you posted your question:
11-18-2012 04:45 PM