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izumi.asakura
Visitor
Visitor
369 Views
Registered: ‎11-05-2018

Vivado HLS causes "Wrong pragma usage" error with a project containing .clang-tidy

(This is a bug report. I don't need support.)

 

I run Vivado HLS in a project with the following directory structure.

my-project
├── .clang-tidy
└── src
    ├── test.cc
    ├── test.h
    ├── test_tb.cc
    └── test_sim.tcl

 

 

The following are the contents of each files.

.clang-tidy

---
Checks: '-*,modernize-use-override,performance-move-const-arg,modernize-use-emplace,performance-noexcept-move-constructor,performance-unnecessary-value-param,performance-unnecessary-copy-initialization,performance-trivially-destructible,bugprone-parent-virtual-call,bugprone-macro-parenthesis,bugprone-string-constructor,bugprone-sizeof-expression'
WarningsAsErrors: '*'
HeaderFilterRegex: '(?!.*pybind11.*).*$'
AnalyzeTemporaryDtors: false
FormatStyle: 'file'
...

test.cc

#include "test.h"

void inc(int in[N], int out[N]) {
    for (int i = 0; i < N; ++i) {
        out[i] = in[i] +  1;
    }
}

test.h

static const int N = 100;

void inc(int in[N], int out[N]);

test_tb.cc

#include <cassert>
#include <iostream>

#include "test.h"

int main() {
    int in[100], out[100];
    for (int i = 0; i < 100; ++i) {
        in[i] = i;
    }
    inc(in, out);
    for (int i = 0; i < 100; ++i) {
        assert(out[i] = in[i] + 1);
    }
}

test_tb.tcl

open_project -reset incr_project
add_files -tb test_tb.cc
add_files -tb test.h
add_files test.cc
set_top inc
open_solution -reset solution1
set_part {xc7z020clg484-1}
create_clock -period 6.66
csynth_design
cosim_design -trace_level all
exit

When running cosim by "vivado_hls -f test_sim.tcl", Vivado HLS caused the following error.

 

INFO: [HLS 200-10] In directory '/home/izumi.asakura/dev/my-project/src'
Sourcing Tcl script 'test_sim.tcl'
INFO: [HLS 200-10] Opening and resetting project '/home/izumi.asakura/dev/my-project/src/incr_project'.
INFO: [HLS 200-10] Adding test bench file 'test_tb.cc' to the project
INFO: [HLS 200-10] Adding test bench file 'test.h' to the project
INFO: [HLS 200-10] Adding design file 'test.cc' to the project
INFO: [HLS 200-10] Opening and resetting solution '/home/izumi.asakura/dev/my-project/src/incr_project/solution1'.
INFO: [HLS 200-10] Cleaning up the solution database.
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg484-1'
INFO: [SYN 201-201] Setting up clock 'default' with a period of 6.66ns.
INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [HLS 200-10] Analyzing design file 'test.cc' ...
Wrong pragma usage.
    while executing
"source test_sim.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $arg] "

INFO: [Common 17-206] Exiting vivado_hls at Wed Nov  4 21:11:37 2020...

When I removed .clang-tidy, synthesis & simulation finished correctly.

I tried Vivado HLS version 2018.3, 2019.2, and 2020.1. The same behavior was reproduced in all versions.

 

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1 Reply
aoifem
Moderator
Moderator
303 Views
Registered: ‎11-21-2018

Thanks @izumi.asakura 

We really appreciate users informing us about bugs. 

I will try to reproduce this, and flag it with development if it is reproduceable. 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


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