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Registered: ‎02-09-2019

Vivado HLS cosimulation of a code running into infinite loop with a warning “Range is empty(null)” and “ The OPMODE 0110X0X with CARRYINSEL”

I am trying to implement a simple demosaic algorithm on hardware using vivado_hls. The c simulation and the synthesis is running successfully. when I run the RTL simulation, at first it is giving me a warning saying:

Starting static elaboration
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/mult_gen_v12_0/hdl/mult_gen_v12_0_vh_rfs.vhd:2255]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/mult_gen_v12_0/hdl/mult_gen_v12_0_vh_rfs.vhd:2240]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/floating_point_v7_1/hdl/floating_point_v7_1_vh_rfs.vhd:90362]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/floating_point_v7_1/hdl/floating_point_v7_1_vh_rfs.vhd:12604]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/floating_point_v7_1/hdl/floating_point_v7_1_vh_rfs.vhd:12604]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_

I don't understand what the warning range is empty means.

Then it says finished, static elaboration and goes on to compiling packages, architecture, and module. After this it enters the vivado simulator and gives me a warning saying:

Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U1/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U2/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U3/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U4/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U5/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U6/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 175 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U15/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 175 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U16/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 175 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U17/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 31065 ns  Iteration: 12  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U1/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 31065 ns  Iteration: 12  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U2/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 31225 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U15/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 31225 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U16/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 31225 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U17/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 81675 ns  Iteration: 12  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U3/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 81715 ns  Iteration: 12  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U5/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 81735 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U3/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.

And this keeps on going for more than an hour.

I am not sure of what this means, I tried looking up the forum regarding this error, but I didn't find much information over there.

I have attached the source code below

core(synthasizable part)

#include "demosiac_h.cpp"
#define min_def(x,y) ( (x)>(y) ? (y) : (x) )
#define max_def(x,y) ( (x)>(y) ? (x) : (y) )

pixel_8 demosiac_interpol(float win[3][3], int r, int c)
{
#pragma HLS PIPELINE II=1
#pragma HLS ARRAY_RESHAPE variable=win complete dim=1

    pixel_f new_pix; //i=col,j=rows
    pixel_8 new_pix_8;
    if (r % 2 == 0 && c % 2 == 0)
    {
        new_pix.r = (win[1][0] + win[1][2]) / 2;
        new_pix.g = win[1][1] * 2;
        new_pix.b = (win[0][1] + win[2][1]) / 2;
    }
    else if (r % 2 == 0 && c % 2 == 1)
    {
        new_pix.r = win[1][1];
        new_pix.g = (win[1][0] + win[2][1] + win[0][1] + win[1][2]) / 2;
        new_pix.b = (win[2][0] + win[0][2] + win[2][2] + win[0][0]) / 4;

    }
    else if (r % 2 == 1 && c % 2 == 0)//blue
    {
        new_pix.r = (win[0][2] + win[2][0] + win[2][2] + win[0][0]) / 4;
        new_pix.g = (win[1][0] + win[1][2] + win[2][1] + win[2][1]) / 2;
        new_pix.b = win[1][1];
    }
    else
    {
        new_pix.r = (win[0][1] + win[2][1]) / 2;
        new_pix.g = win[1][1] * 2;
        new_pix.b = (win[1][0] + win[1][2]) / 2;
    }
    new_pix_8.r =uc(max_def(min_def((new_pix.r*255.0),255.0),0.0));
    new_pix_8.g =uc(max_def(min_def((new_pix.g*255.0),255.0),0.0));
    new_pix_8.b =uc(max_def(min_def((new_pix.b*255.0),255.0),0.0));

    return new_pix_8;

}
void demosiac_filter(Stream_t& in,Stream_t& out)
{
#pragma HLS INTERFACE axis port=in
#pragma HLS INTERFACE axis port=out
//#pragma HLS INTERFACE s_axilite port=return   bundle=CONTROL_BUS

    //#pragma HLS INTERFACE s_axilite port=rows     bundle=CONTROL_BUS //offset=0x14
    //#pragma HLS INTERFACE s_axilite port=cols     bundle=CONTROL_BUS //offset=0x1C
    //#pragma HLS INTERFACE ap_stable port=rows
    //#pragma HLS INTERFACE ap_stable port=cols
#pragma HLS dataflow
//#pragma HLS inline
    uc pin,pout;
    float input_pix;
    float window[3][3];

    float line_buf[2][514];
#pragma HLS ARRAY_PARTITION variable=line_buf complete dim=1
    pixel_8 out_pix;
    outer_loop:for(int row=0; row<258;row++)
//#pragma HLS PIPELINE II=1
        {
        inner_loop:for(int col=0; col<514;col++)
            {
#pragma HLS PIPELINE II=1
                in >> pin;
                input_pix = ((float)pin)/256.0;
                window_loop:for (int i = 0; i < 3; i++)
                {
#pragma HLS UNROLL
                    window[i][0] = window[i][1];
                    window[i][1] = window[i][2];
                }
                window[0][2] = line_buf[0][col];
                window[1][2] = line_buf[0][col] = line_buf[1][col];
                window[2][2] = line_buf[1][col] = input_pix;

                if (row > 1 && col > 1 && row < 258  && col < 514 )
                {
                    out_pix = demosiac_interpol(window, row - 2, col - 2);
                    out<<out_pix.r;
                    out<<out_pix.g;
                    out<<out_pix.b;
                }

            }
        }

}

Testbench:

Stream_t in("in_tb"),out("out_tb");
    for(int i=0; i<258;i++)
    {
        for(int j=0; j<514;j++)
        {
            in<<input[i][j];

        }
    }
    demosiac_filter(in,out);
    for(int i=0; i<256;i++)
        {
            for(int j=0; j<512;j++)
            {
                for(int k=0; k<3 ; k++)
                {
                    final_img[i][j][k]= out.read();
                }
            }
        }

header(demosiac_h.cpp):

//#include "ap_fixed.h"
#include "hls_stream.h"
typedef unsigned char uc;
typedef hls::stream<uc> Stream_t;
void demosiac_filter(Stream_t& in,Stream_t& out);
struct pixel_f
{
    float r;
    float g;
    float b;
};

struct pixel_8
{
    uc r;
    uc g;
    uc b;
};

I have been stuck at this issue for almost a week. Cannot pinpoint what exactly the issue is!! I have attached the complete cosim report, 

Any Help/suggestion in debugging this issue will be highly appreciated

Thanks in advance

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