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julian.spahr
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Registered: ‎06-28-2018

Vivado HLS generated IP takes one execution for new AXI-Lite parameters to take effect

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Hello everyone,

My name is Julian! I've been working for years with the Vivado Design Suite but as of recently, I've come back to use Vivado HLS to save design time. However, despite the amounts of documentation about the design suite, I have come across a few problems.

The setup: I have generated a Vivado HLS AXI-Stream IP (it has both a master and a slave side), that is configurable (also, a couple of AXI-Lite defined parameters). I'm working on a Zynq UltraScale+, that I have connected to my pc using LWIP.

The IP itself gets configured once data has arrived from my PC (as a side note, I use Matlab for that). I send both configuration data, as well as the payload to be processed. Now, I send data, the IP configures itself, a DMA transfer happens, and the result is sent back. Basically, the IP is configured once for every data transfer from Matlab to ZUSC. Now the question:

* The first time I sent data to both configure and execute the HW processor, its parameters are set correctly. The accelerator is executed, data is produced, and it is 100 % correct, compared to my Matlab implementation. However: if I chain these executions, which is I change one of the parameters, the HW accelerator requieres 1 extra execution for the new parameter to take effect. E.g.: I set the IP and configure it for N amount of data which is truncated with value T. First execution after the SoC reset runs fine, but if I then change the truncation to another value, let's say T+1, the first execution returns data with value T, and the second with T+1. Everything on after that truncates with T+1 but I have that one execution at the start which is messing with my implementation.

Things that I have tried: enabling autorestart and allow for transparent executions; or disable autorestart and starting the IP with every new execution; I use the hls::stream class for my AXI-Stream and have tried both .read() and .read_nb() functions to see whether or not there is a difference; setting the IP to ap_ctrl_none, such that the SW driver only contains initializers, and getters/setters for my AXI-Lite parameters (no IP start, no enable/disable autorestart).

Now, the final implementation requires this IP to live alongside PL-only logic (basically two custom IPs on either side), and the idea that I would need one execution per reconfiguration, is not acceptable.

Which begs a couple of questions:

* What am I doing wrong?

* Is the IP operating correctly and am I not considering something that I should?

* Does it have something to do with my implementation? I can (and will) post a snippet of my HLS code later. For now I can tell you that it is a switch-case statement that evaluates the IP mode (AXI-Lite parameter), and inside each mode you would find a different set of AXI-Stream operations, limited in its length by other AXI-Lite parameters (for example, number of elements to be read from the slave or written to the master).

* Do I need to get rid of the "mode" parameter

My whole problem boils down to this:

Why does hot-reconfiguration require a function call (or IP execution) before taking effect? Or even, why does the first configuration work fine, but reconfiguration lags behind one IP execution?

Thank you very much in advance for your time.

Regards,

Julian

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julian.spahr
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Registered: ‎06-28-2018

I have found the reason for my problem, but not a solution.

My IP block was INDEED in Autorestart mode. Thus, if I want to change a parameters value once a transaction has already started, I will need to finish that transaction (AXIS transfer for example). That last transaction though, will require the old param values. I.e., if my hardware accelerator is able to consume variable amounts of data, depending on a configuration parameter, and I set it from 4096 to 1024, it will require 1 last 4096 elements stream consumption for it to take effect.

My work around for now is use the ap_rst_n signal of my HLS IP: I "intercept" the global RST signal with an AND gate. The AND gate has the global RST_N as an input on one side, and a GPIO on the other, such that I can write by Xil_Out32 a RST value onto that address.

Basically I will reset the IP from software using a GPIO IP block, in the hopes that the IP is reset properly, so that it escapes the last transaction it has to go through, which I cannot afford in my design. 

I'd rather reset and reconfig that having to ask for one more AXI-Stream transaction. 

A bold solution if you ask me...

 

Cheers to anybody who's read this.

View solution in original post

1 Reply
julian.spahr
Participant
Participant
1,027 Views
Registered: ‎06-28-2018

I have found the reason for my problem, but not a solution.

My IP block was INDEED in Autorestart mode. Thus, if I want to change a parameters value once a transaction has already started, I will need to finish that transaction (AXIS transfer for example). That last transaction though, will require the old param values. I.e., if my hardware accelerator is able to consume variable amounts of data, depending on a configuration parameter, and I set it from 4096 to 1024, it will require 1 last 4096 elements stream consumption for it to take effect.

My work around for now is use the ap_rst_n signal of my HLS IP: I "intercept" the global RST signal with an AND gate. The AND gate has the global RST_N as an input on one side, and a GPIO on the other, such that I can write by Xil_Out32 a RST value onto that address.

Basically I will reset the IP from software using a GPIO IP block, in the hopes that the IP is reset properly, so that it escapes the last transaction it has to go through, which I cannot afford in my design. 

I'd rather reset and reconfig that having to ask for one more AXI-Stream transaction. 

A bold solution if you ask me...

 

Cheers to anybody who's read this.

View solution in original post